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lynxpoint: update MBP give up routine 

I'm not sure if I screwed this up originally or the Intel docs changed
(I didn't bother to go back and check). According to ME BWG 1.1.0 the give
up bit is in the host general status #2 register.

Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2808
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Aaron Durbin 2013-02-25 10:51:52 -06:00 committed by Ronald G. Minnich
parent b86113fd9a
commit b37d1fb95a
2 changed files with 1 additions and 3 deletions
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2
src/southbridge/intel/lynxpoint/me.h
View File

@ -201,8 +201,6 @@ struct me_hfs2 {
#define PCI_ME_H_GS2 0x70 #define PCI_ME_H_GS2 0x70
#define PCI_ME_MBP_GIVE_UP 0x01 #define PCI_ME_MBP_GIVE_UP 0x01
#define PCI_ME_H_GS3 0x74
#define PCI_ME_HERES 0xbc #define PCI_ME_HERES 0xbc
#define PCI_ME_EXT_SHA1 0x00 #define PCI_ME_EXT_SHA1 0x00
#define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_EXT_SHA256 0x02

2
src/southbridge/intel/lynxpoint/me_9.x.c
View File

@ -804,7 +804,7 @@ static void intel_me_mbp_give_up(device_t dev)
struct mei_csr csr; struct mei_csr csr;
reg32 = PCI_ME_MBP_GIVE_UP; reg32 = PCI_ME_MBP_GIVE_UP;
pci_write_config32(dev, PCI_ME_H_GS3, reg32); pci_write_config32(dev, PCI_ME_H_GS2, reg32);
read_host_csr(&csr); read_host_csr(&csr);
csr.reset = 1; csr.reset = 1;
csr.interrupt_generate = 1; csr.interrupt_generate = 1;