mb/google/puff/var/dooly: update USB2 type-c strength
Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
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@ -27,7 +27,14 @@ chip soc/intel/cannonlake
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 0
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}" # Type-A Port 0
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0
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register "usb2_ports[1]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-C Port 0
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register "usb2_ports[2]" = "{
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register "usb2_ports[2]" = "{
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.enable = 1,
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.enable = 1,
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.ocpin = OC3,
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.ocpin = OC3,
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@ -37,7 +44,14 @@ chip soc/intel/cannonlake
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 1
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}" # Type-A Port 1
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1
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register "usb2_ports[4]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_28P15MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-C Port 1
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register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam
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register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam
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register "usb2_ports[6]" = "USB2_PORT_EMPTY"
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register "usb2_ports[6]" = "USB2_PORT_EMPTY"
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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register "usb2_ports[7]" = "USB2_PORT_EMPTY"
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