drivers/intel/fsp2_0: Add coreboot<->FSP header files
This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/13796 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -14,5 +14,6 @@
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##
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##
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source src/drivers/intel/fsp1_1/Kconfig
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source src/drivers/intel/fsp1_1/Kconfig
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source src/drivers/intel/fsp2_0/Kconfig
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source src/drivers/intel/gma/Kconfig
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source src/drivers/intel/gma/Kconfig
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source src/drivers/intel/i210/Kconfig
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source src/drivers/intel/i210/Kconfig
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@ -2,4 +2,5 @@ subdirs-y += gma
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subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi
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subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi
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subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0
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subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0
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subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1
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subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1
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subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0
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subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210
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subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210
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@ -0,0 +1,6 @@
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config PLATFORM_USES_FSP2_0
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bool
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help
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Include FSP 2.0 wrappers and functionality
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@ -0,0 +1,11 @@
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romstage-y += hand_off_block.c
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romstage-y += util.c
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romstage-y += memory_init.c
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ramstage-y += graphics.c
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ramstage-y += hand_off_block.c
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ramstage-y += notify.c
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ramstage-y += silicon_init.c
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ramstage-y += util.c
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CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _FSP2_0_API_H_
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#define _FSP2_0_API_H_
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#include <stddef.h>
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#include <memrange.h>
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#include <fsp/info_header.h>
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enum fsp_status {
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FSP_SUCCESS = 0x00000000,
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FSP_INVALID_PARAMETER = 0x80000002,
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FSP_UNSUPPORTED = 0x80000003,
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FSP_NOT_READY = 0x80000006,
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FSP_DEVICE_ERROR = 0x80000007,
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FSP_OUT_OF_RESOURCES = 0x80000009,
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FSP_VOLUME_CORRUPTED = 0x8000000a,
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FSP_NOT_FOUND = 0x8000000a,
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FSP_TIMEOUT = 0x80000012,
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FSP_ABORTED = 0x80000015,
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FSP_INCOMPATIBLE_VERSION = 0x80000010,
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FSP_SECURITY_VIOLATION = 0x8000001a,
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FSP_CRC_ERROR = 0x8000001b,
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};
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enum fsp_notify_phase {
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AFTER_PCI_ENUM = 0x20,
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READY_TO_BOOT = 0x40
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};
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/* Opaque structures. These are platform-specific. */
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struct FSP_M_CONFIG;
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struct FSP_S_CONFIG;
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/* Main FSP stages */
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enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r);
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enum fsp_status fsp_silicon_init(struct range_entry *r);
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enum fsp_status fsp_notify(enum fsp_notify_phase phase);
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/* Callbacks for updating stage-specific parameters */
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void platform_fsp_memory_init_params_cb(struct fsp_m_arch_upd *archupd,
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struct FSP_M_CONFIG *mcfg);
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void platform_fsp_silicon_init_params_cb(struct FSP_S_CONFIG *silupd);
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/*
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* # DOCUMENTATION:
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*
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* This file defines the interface between coreboot and the FSP 2.0 wrapper
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* fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry
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* points and map 1:1 to the FSP entry points of the same name.
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*
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* ### fsp_memory_init():
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* - hob_list: retuns a pointer to the HOB storage area created by FSP
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* - r: memory range that the binary is allowed to be loaded into
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*
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* This function is responsible for loading and executing the memory
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* initialization code from the FSP-M binary. It expects this binary to reside
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* in cbfs as FSP_M_FILE.
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*
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* The function takes one parameter, which is described below, but does not
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* take in memory parameters as an argument. The memory parameters can be filled
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* in with platform_fsp_memory_init_params_cb(). This is a callback symbol
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* that fsp_memory_init() will call. The platform must provide this symbol.
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*
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* FSP returns information about the memory layout in a series of structures
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* called hand-off-blocks (HOB). The "hob_list" output parameter will point to
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* the start of the HOB list. The fsp reserved region will also be described by
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* one of the HOBs. For more information on parsing these structures, see
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* fsp/util.h
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*
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*
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* ### fsp_silicon_init():
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* - r: memory range that the binary is allowed to be loaded into
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*
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* This function is responsible for loading and executing the silicon
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* initialization code from the FSP-S binary. It expects this binary to reside
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* in cbfs as FSP_S_FILE.
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*
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* Like fsp_memory_init(), it provides a callback to fill in FSP-specific
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* parameters, via platform_fsp_silicon_init_params_cb(). The platform must
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* also provide this symbol.
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*
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*
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* ### fsp_notify():
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* - phase: Which FSP notification phase
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*
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* This function is responsible for loading and executing the notify code from
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* the FSP-S binary. It expects that fsp_silicon_init() has already been called
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* succesfully, and that the FSP-S binary is still loaded into memory.
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*/
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#endif /* _FSP2_0_API_H_ */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _FSP2_0_INFO_HEADER_H_
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#define _FSP2_0_INFO_HEADER_H_
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#include <rules.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <types.h>
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#define FSP_HDR_OFFSET 0x94
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#define FSP_HDR_LEN 0x48
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#define FSP_HDR_SIGNATURE "FSPH"
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#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28)
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#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28)
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#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28)
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struct fsp_header {
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uint32_t fsp_revision;
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size_t image_size;
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uintptr_t image_base;
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uint32_t image_attribute;
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size_t cfg_region_offset;
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size_t cfg_region_size;
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size_t notify_phase_entry_offset;
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size_t memory_init_entry_offset;
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size_t silicon_init_entry_offset;
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char image_id[sizeof(uint64_t) + 1];
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uint8_t revision;
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};
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struct fsp_upd_header {
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uint64_t signature;
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uint8_t revision;
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};
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struct fsp_m_arch_upd {
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uint8_t revision;
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uintptr_t nvs_buffer;
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uintptr_t stack_base;
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uint32_t stack_size;
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uint32_t bootloader_tolumsz;
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uint32_t boot_mode;
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};
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enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
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void fsp_print_header_info(const struct fsp_header *hdr);
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void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob);
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#if ENV_RAMSTAGE
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/*
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* This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains
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* both SiliconInit and Notify APIs. When SiliconInit is loaded the
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* header is saved so that when Notify is called we do not have to start
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* header parsing again.
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*/
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extern struct fsp_header fsps_hdr;
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#endif
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#endif /* _FSP2_0_INFO_HEADER_H_ */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _FSP2_0_UTIL_H_
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#define _FSP2_0_UTIL_H_
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#include <boot/coreboot_tables.h>
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#include <fsp/info_header.h>
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#include <device/resource.h>
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#include <memrange.h>
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/*
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* Hand-off-block handling functions that depend on CBMEM, and thus can only
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* be used after cbmem_initialize().
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*/
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void fsp_save_hob_list(void *hob_list_ptr);
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const void *fsp_get_hob_list(void);
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const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size);
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enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
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/*
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* Hand-off-block utilities which do not depend on CBMEM, but need to be passed
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* the HOB list explicitly.
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*/
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void fsp_find_reserved_memory(struct resource *res, const void *hob_list);
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void fsp_print_memory_resource_hobs(const void *hob_list);
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/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */
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enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name,
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struct range_entry *r);
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/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */
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uintptr_t fsp_load_vbt(void);
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#endif /* _FSP2_0_UTIL_H_ */
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