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AGESA f15tn: Fix building IDS tracing support 

Also add a config file to ensure the code gets build-tested.

Change-Id: I530eccd2a194bc79de5ee354d98260d93423cd5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53986
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-05-09 16:11:30 +02:00 committed by David Hendricks
parent 02d9c85e75
commit b382b890f8
17 changed files with 44 additions and 38 deletions
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7
configs/config.asus_a88xm-e.agesa_debug Normal file
View File

@ -0,0 +1,7 @@
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_A88XM_E=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_IDS_TRACING_ENABLED=y
CONFIG_AGESA_EXTRA_TIMESTAMPS=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
CONFIG_DEBUG_RESOURCES=y

18
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15MmioMap.c
View File

@ -147,10 +147,8 @@ cpuF15AddingMmioMap (
MmioRange[MmioPair].RangeNum = MmioPair;
MmioRange[MmioPair].Modified = FALSE;
IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
MmioRange[MmioPair].Base & 0xFFFFFFFF,
(MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
MmioRange[MmioPair].Limit & 0xFFFFFFFF);
IDS_HDT_CONSOLE (MAIN_FLOW, "%016llx %016llx", MmioRange[MmioPair].Base,
MmioRange[MmioPair].Limit);
IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N",
MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N",
MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N",
@ -164,10 +162,8 @@ cpuF15AddingMmioMap (
NewMmioRange.Base = AmdAddMmioParams.BaseAddress;
NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length + 0x10000;
NewMmioRange.Attribute = AmdAddMmioParams.Attributes;
IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF,
NewMmioRange.Base & 0xFFFFFFFF,
(NewMmioRange.Limit >> 32) & 0xFFFFFFFF,
NewMmioRange.Limit & 0xFFFFFFFF);
IDS_HDT_CONSOLE (MAIN_FLOW, "req %016llx %016llx\n", NewMmioRange.Base,
NewMmioRange.Limit);
for (ConfMapRange = 0; ConfMapRange < CONF_MAP_NUM; ConfMapRange++) {
PciAddress.Address.Register = (CONF_MAP_RANGE_0 + ConfMapRange * 4);
LibAmdPciRead (AccessWidth32, PciAddress, &ConfMapRegister, &(AmdAddMmioParams.StdHeader));
@ -298,10 +294,8 @@ cpuF15AddingMmioMap (
PciAddress.Address.Function = FUNC_1;
for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
MmioRange[MmioPair].Base & 0xFFFFFFFF,
(MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
MmioRange[MmioPair].Limit & 0xFFFFFFFF);
IDS_HDT_CONSOLE (MAIN_FLOW, "%016llx %016llx", MmioRange[MmioPair].Base,
MmioRange[MmioPair].Limit);
IDS_HDT_CONSOLE (MAIN_FLOW, " %s %s %s %s", MmioRange[MmioPair].Attribute.MmioPostedRange ? "Y" : "N",
MmioRange[MmioPair].Attribute.MmioReadableRange ? "Y" : "N",
MmioRange[MmioPair].Attribute.MmioWritableRange ? "Y" : "N",

2
src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitReset.c
View File

@ -155,7 +155,7 @@ AmdInitReset (
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString);
IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (char *)&UserOptions.VersionString);
AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
ASSERT (ResetParams != NULL);

2
src/vendorcode/amd/agesa/f15tn/Proc/Common/S3RestoreState.c
View File

@ -165,7 +165,7 @@ S3RestoreStateFromTable (
PCI_ADDR PciAddress;
UINTN Index;
S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER);
IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n");
while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) {
switch (*(UINT16 *) S3SaveTableRecordPtr) {
case SAVE_STATE_IO_WRITE_OPCODE:

8
src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c
View File

@ -268,7 +268,7 @@ S3SaveStateSaveWriteOp (
}
}
S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width);
IDS_HDT_CONSOLE (S3_TRACE, "\n");
);
@ -333,7 +333,7 @@ S3SaveStateSaveReadWriteOp (
}
}
S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
@ -409,7 +409,7 @@ S3SaveStateSavePollOp (
}
}
S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: %s Address: 0x%016llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
@ -481,7 +481,7 @@ S3SaveStateSaveInfoOp (
SaveOffsetPtr->OpCode = OpCode;
SaveOffsetPtr->Length = InformationLength;
S3_SCRIPT_DEBUG_CODE (
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %s \n", Information);
IDS_HDT_CONSOLE (S3_TRACE, " S3 Save: Info: %p\n", Information);
);
LibAmdMemCopy (
(UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),

2
src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitEnvDef.c
View File

@ -139,7 +139,7 @@ FchInitEnvCreatePrivateData (
FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr;
ASSERT (FchParams != NULL);
IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = %p\n", AgesaStatus, FchParams);
// Load private data block with default
*FchParams = InitEnvCfgDefault;

2
src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/InitResetDef.c
View File

@ -71,7 +71,7 @@ FchInitResetLoadPrivateDefault (
FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr;
ASSERT (FchParams != NULL);
IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FCH Reset Data Block Allocation: [0x%x], Ptr = %p\n", AgesaStatus, FchParams);
*FchParams = InitResetCfgDefault;

2
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
View File

@ -473,7 +473,7 @@ GnbLibDebugDumpBuffer (
Index += 4;
break;
case 4:
IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4));
IDS_HDT_CONSOLE (GNB_TRACE, "%016llx", *(UINT64 *) ((UINT8 *) Buffer + Index));
Index += 8;
break;
default:

2
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
View File

@ -223,7 +223,7 @@ GfxConfigDebugDump (
);
IDS_HDT_CONSOLE (GFX_MISC, " UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA");
if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase);
IDS_HDT_CONSOLE (GFX_MISC, " UmaBase - 0x%llx\n", Gfx->UmaInfo.UmaBase);
IDS_HDT_CONSOLE (GFX_MISC, " UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize);
IDS_HDT_CONSOLE (GFX_MISC, " UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes);
}

8
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
View File

@ -895,7 +895,7 @@ GfxIntegratedDebugDumpPpTable (
ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
IDS_HDT_CONSOLE (GFX_MISC, " < --- SW State Table ---------> \n");
for (Index = 0; Index < StateArray->ucNumEntries; Index++) {
IDS_HDT_CONSOLE (GFX_MISC, " State #%d\n", Index + 1
IDS_HDT_CONSOLE (GFX_MISC, " State #%ld\n", Index + 1
);
IDS_HDT_CONSOLE (GFX_MISC, " Classification 0x%x\n",
NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification
@ -922,7 +922,7 @@ GfxIntegratedDebugDumpPpTable (
for (Index = 0; Index < ClockInfoArrayPtr->ucNumEntries; Index++) {
UINT32 Sclk;
Sclk = ClockInfoArrayPtr->ClockInfo[Index].usEngineClockLow | (ClockInfoArrayPtr->ClockInfo[Index].ucEngineClockHigh << 16);
IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%d\n",
IDS_HDT_CONSOLE (GFX_MISC, " DPM State #%ld\n",
Index
);
IDS_HDT_CONSOLE (GFX_MISC, " SCLK = %d\n",
@ -951,7 +951,7 @@ GfxIntegratedDebugDumpPpTable (
for (Index = 0; Index < VceStateTable->numEntries; Index++) {
SclkIndex = VceStateTable->entries[Index].ucClockInfoIndex & 0x3F;
EclkIndex = VceStateTable->entries[Index].ucVCEClockInfoIndex;
IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%d\n", Index
IDS_HDT_CONSOLE (GFX_MISC, " VCE State #%ld\n", Index
);
if ((VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)) == 0) {
IDS_HDT_CONSOLE (GFX_MISC, " Disable\n");
@ -973,7 +973,7 @@ GfxIntegratedDebugDumpPpTable (
IDS_HDT_CONSOLE (GFX_MISC, " < --- VCE Voltage Record Table ---> \n");
for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) {
EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex;
IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%d\n", Index
IDS_HDT_CONSOLE (GFX_MISC, " VCE Voltage Record #%ld\n", Index
);
IDS_HDT_CONSOLE (GFX_MISC, " ECLK = %d\n",
VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)

2
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
View File

@ -337,7 +337,7 @@ GnbTjOffsetUpdateTN (
ASSERT (GnbHandle != NULL);
GetLogicalIdOfSocket (GnbGetSocketId (GnbHandle), &LogicalId, StdHeader);
if ((LogicalId.Revision & 0x0000000000000100ull ) != 0x0000000000000100ull ) {
IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %x, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision);
IDS_HDT_CONSOLE (GNB_TRACE, "CPU Rev = %llx, Skip GnbTjOffsetUpdateTN\n", LogicalId.Revision);
return;
}
GnbRegisterReadTN (D0F0xBC_xE0104040_TYPE, D0F0xBC_xE0104040_ADDRESS, &D0F0xBC_xE0104040, 0, StdHeader);

4
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
View File

@ -888,7 +888,7 @@ GnbFuseTableDebugDumpTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINTN Index;
UINT32 Index;
IDS_HDT_CONSOLE (NB_MISC, "<------------ GNB FUSE TABLE------------>\n");
for (Index = 0; Index < 4; Index++) {
@ -945,7 +945,7 @@ GnbFuseTableDebugDumpTN (
);
IDS_HDT_CONSOLE (
NB_MISC,
" VCE Flags[ % d] - 0x % 02x\n",
" VCE Flags[%d] - 0x%02x\n",
Index,
PpFuseArray->VceFlags[Index]
);

2
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c
View File

@ -292,7 +292,7 @@ GnbIommuIvrsTableDump (
Entry = Entry + 4;
break;
default:
IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n");
IDS_HDT_CONSOLE (GNB_TRACE, " Unsupported entry type [%d]\n", *Entry);
ASSERT (FALSE);
}
}

2
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
View File

@ -578,7 +578,7 @@ GnbEnableIommuMmioV4 (
BaseAddress |= Value;
if ((BaseAddress & 0xfffffffffffffffe) != 0x0) {
IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
IDS_HDT_CONSOLE (GNB_TRACE, " Enable IOMMU MMIO at address %llx for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader);
GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader);
} else {

13
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
View File

@ -557,7 +557,10 @@ PcieConfigEngineDebugDump (
EngineList->Type.Port.Address.Address.Device,
EngineList->Type.Port.Address.Address.Function
);
IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls);
IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Compliance Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkComplianceMode);
IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, Safe Mode - %u\n", EngineList->Type.Port.PortData.MiscControls.LinkSafeMode);
IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, SB Link - %u\n", EngineList->Type.Port.PortData.MiscControls.SbLink);
IDS_HDT_CONSOLE (PCIE_MISC, " Misc Control, CLK PM Support - %u\n", EngineList->Type.Port.PortData.MiscControls.ClkPmSupport);
IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Dev Number - %d\n", EngineList->Type.Port.NativeDevNumber);
IDS_HDT_CONSOLE (PCIE_MISC, " Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber);
IDS_HDT_CONSOLE (PCIE_MISC, " Hotplug - %s\n",
@ -737,7 +740,7 @@ PcieUserDescriptorConfigDump (
EngineDescriptor->EngineData.EndLane
);
if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n SB link - %d\n MiscControls - 0x%02x\n" ,
IDS_HDT_CONSOLE (PCIE_MISC, " PortPresent - %d\n ChannelType - %d\n DeviceNumber - %d\n FunctionNumber - %d\n LinkSpeedCapability - %d\n LinkAspm - %d\n LinkHotplug - %d\n ResetId - %d\n Compliance Mode - %d\n Safe Mode - %d\n SB link - %d\n CLK PM Support - %d\n" ,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber,
@ -746,8 +749,10 @@ PcieUserDescriptorConfigDump (
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkComplianceMode,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkSafeMode,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink,
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls
((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.ClkPmSupport
);
}
if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
@ -785,7 +790,7 @@ PcieUserConfigConfigDump (
for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) {
CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex);
NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor);
IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %d\n",
IDS_HDT_CONSOLE (PCIE_MISC, " ComplexDescriptor SocketId - %d\n NumberOfEngines - %ld\n",
ComplexDescriptor->SocketId,
NumberOfEngines
);

4
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c
View File

@ -167,7 +167,7 @@ PcieLanesToPowerDownPllInL1 (
for (Index = 0; Index < 4; Index++) {
if ((ActiveLanesBitmap & (0xF << (Index * 4))) != 0) {
if (LaneGroupExitLatency [Index] > LinkLatencyInfo.MaxL1ExitLatency) {
IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Latency %d\n", Index, LinkLatencyInfo.MaxL1ExitLatency);
LaneGroupExitLatency [Index] = LinkLatencyInfo.MaxL1ExitLatency;
}
}
@ -177,7 +177,7 @@ PcieLanesToPowerDownPllInL1 (
}
LaneBitmapForPllOffInL1 = 0;
for (Index = 0; Index < 4; Index++) {
IDS_HDT_CONSOLE (GNB_TRACE, " Index %d Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
IDS_HDT_CONSOLE (GNB_TRACE, " Index %ld Final Latency %d\n", Index, LaneGroupExitLatency[Index]);
if (LaneGroupExitLatency[Index] > PllPowerUpLatency) {
LaneBitmapForPllOffInL1 |= (0xF << (Index * 4));
}

2
src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c
View File

@ -442,7 +442,7 @@ MemSPDDataProcess (
AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader);
if (AgesaStatus == AGESA_SUCCESS) {
DimmSPDPtr->DimmPresent = TRUE;
IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer);
IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %p\n", Socket, Channel, Dimm, SpdParam.Buffer);
#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM))
AgesaCustomMemoryProfileSPD(SpdParam.Buffer);
#endif