diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 975afc9e26..28e7b83386 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -27,22 +27,25 @@ config PCR_BASE_ADDRESS
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xfe8b0000
+	default 0xfe800000
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x170000
+	default 0x1fff00
 	help
 	  The size of the cache-as-ram region required during bootblock
-	  and/or romstage.
+	  and/or romstage. FSP-T reserves the upper 0x100 for
+	  FspReservedBuffer.
 
 config DCACHE_BSP_STACK_SIZE
 	hex
-	default 0xA0000
+	default 0x140000
 	help
 	  The amount of anticipated stack usage in CAR by bootblock and
 	  other stages. It needs to include FSP-M stack requirement and
-	  CB romstage stack requirement.
+	  CB romstage stack requirement. The integration documentation
+	  says this needs to be 256KiB, but practice show this needs to
+	  be a lot more.
 
 config CPU_MICROCODE_CBFS_LOC
 	hex
@@ -67,11 +70,13 @@ config STACK_SIZE
 config FSP_TEMP_RAM_SIZE
 	hex
 	depends on FSP_USES_CB_STACK
-	default 0xA0000
+	default 0x40000
 	help
 	  The amount of anticipated heap usage in CAR by FSP.
 	  Refer to Platform FSP integration guide document to know
-	  the exact FSP requirement for Heap setup.
+	  the exact FSP requirement for Heap setup.  The FSP integration
+	  documentation says this needs to be at least 128KiB, but practice
+	  show this needs to be 256KiB or more.
 
 config SOC_INTEL_COMMON_BLOCK_P2SB
 	def_bool y