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soc/amd/common: Don't get eSPI address from PCI if not on x86 

Exclude lpc_get_spibase() on the PSP.  This also simplifies the
espi_get_bar() function.

BUG=b:159811539
TEST=Build & boot trembyle; Verify address in PSP & x86

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5927dd40610860b54bb35a7e5b03ddb731597745
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2020-07-14 11:08:55 -06:00 committed by Aaron Durbin
parent 37d1206c6e
commit b39e10dbaa
2 changed files with 2 additions and 9 deletions
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10
src/soc/amd/common/block/lpc/espi_util.c
View File

@ -19,14 +19,8 @@ void espi_update_static_bar(uintptr_t bar)
static uintptr_t espi_get_bar(void) static uintptr_t espi_get_bar(void)
{ {
uintptr_t espi_spi_base; if (ENV_X86 && !espi_bar)
espi_update_static_bar(lpc_get_spibase() + ESPI_OFFSET_FROM_BAR);
if (espi_bar)
return espi_bar;
espi_spi_base = lpc_get_spibase();
espi_update_static_bar(espi_spi_base + ESPI_OFFSET_FROM_BAR);
return espi_bar; return espi_bar;
} }

1
src/soc/amd/picasso/include/soc/iomap.h
View File

@ -6,7 +6,6 @@
/* MMIO Ranges */ /* MMIO Ranges */
/* IO_APIC_ADDR defined in arch/x86 0xfec00000 */ /* IO_APIC_ADDR defined in arch/x86 0xfec00000 */
#define SPI_BASE_ADDRESS 0xfec10000 #define SPI_BASE_ADDRESS 0xfec10000
#define ESPI_BASE_ADDRESS 0xfec20000
#if CONFIG(HPET_ADDRESS_OVERRIDE) #if CONFIG(HPET_ADDRESS_OVERRIDE)
#error HPET address override is not allowed and must be fixed at 0xfed00000 #error HPET address override is not allowed and must be fixed at 0xfed00000