sb,soc/intel: Drop unnecessary headers

Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.

Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/lib/coreboot_table.c

@@ -27,13 +27,6 @@
 #if CONFIG(USE_OPTION_TABLE)
 #include <option_table.h>
 #endif
-#if CONFIG(CHROMEOS)
-#if CONFIG(HAVE_ACPI_TABLES)
-#include <acpi/acpi.h>
-#endif
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-#endif
 #if CONFIG(PLATFORM_USES_FSP2_0)
 #include <fsp/util.h>
 #else

src/mainboard/google/butterfly/early_init.c

@@ -7,9 +7,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#if CONFIG(CHROMEOS)
-#include <vendorcode/google/chromeos/chromeos.h>
-#endif
 
 void mainboard_late_rcba_config(void)
 {

src/soc/intel/baytrail/romstage/raminit.c

@@ -17,8 +17,6 @@
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
 #include <security/vboot/vboot_common.h>
 
 uintptr_t smbus_base(void)

src/soc/intel/baytrail/romstage/romstage.c

@@ -6,9 +6,6 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 #include <cbmem.h>
-#if CONFIG(EC_GOOGLE_CHROMEEC)
-#include <ec/google/chromeec/ec.h>
-#endif
 #include <elog.h>
 #include <romstage_handoff.h>
 #include <string.h>

src/soc/intel/broadwell/acpi.c

@@ -14,8 +14,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/turbo.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>

src/soc/intel/broadwell/cpu/acpi.c

@@ -14,8 +14,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/turbo.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>

src/soc/intel/broadwell/pch/acpi.c

@@ -14,8 +14,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/turbo.h>
-#include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>

src/soc/intel/broadwell/raminit.c

@@ -9,11 +9,6 @@
 #include <memory_info.h>
 #include <mrc_cache.h>
 #include <string.h>
-#if CONFIG(EC_GOOGLE_CHROMEEC)
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#endif
-#include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/iomap.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>

src/southbridge/intel/bd82x6x/me.c

@@ -23,10 +23,6 @@
 #include "me.h"
 #include "pch.h"
 
-#if CONFIG(CHROMEOS)
-#include <vendorcode/google/chromeos/gnvs.h>
-#endif
-
 /* Send END OF POST message to the ME */
 static int __unused mkhi_end_of_post(void)
 {

src/southbridge/intel/bd82x6x/me_8.x.c

@@ -23,10 +23,6 @@
 #include "me.h"
 #include "pch.h"
 
-#if CONFIG(CHROMEOS)
-#include <vendorcode/google/chromeos/gnvs.h>
-#endif
-
 /* Send END OF POST message to the ME */
 static int __unused mkhi_end_of_post(void)
 {