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soc/intel/denverton_ns: Hook up SMMSTORE 

Tested on Intel Harcuvar CRB, SMMSTORE is now working.

Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Angel Pons 2020-11-11 11:26:52 +01:00
parent 8446935d3b
commit b3aaa63e8f
1 changed files with 25 additions and 0 deletions
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25
src/soc/intel/denverton_ns/smihandler.c
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@ -10,6 +10,7 @@
#include <cpu/intel/em64t100_save_state.h>
#include <device/pci_def.h>
#include <intelblocks/fast_spi.h>
#include <smmstore.h>
#include <spi-generic.h>
#include <soc/iomap.h>
#include <soc/soc_util.h>
@ -197,6 +198,26 @@ static void finalize(void)
fast_spi_init();
}
static void southbridge_smi_store(void)
{
u8 sub_command, ret;
em64t100_smm_state_save_area_t *io_smi =
smi_apmc_find_state_save(APM_CNT_SMMSTORE);
uint32_t reg_ebx;
if (!io_smi)
return;
/* Command and return value in EAX */
sub_command = (io_smi->rax >> 8) & 0xff;
/* Parameter buffer in EBX */
reg_ebx = io_smi->rbx;
/* drivers/smmstore/smi.c */
ret = smmstore_exec(sub_command, (void *)reg_ebx);
io_smi->rax = ret;
}
static void southbridge_smi_apmc(void)
{
uint8_t reg8;
@ -245,6 +266,10 @@ static void southbridge_smi_apmc(void)
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
break;
case APM_CNT_SMMSTORE:
if (CONFIG(SMMSTORE))
southbridge_smi_store();
break;
}
mainboard_smi_apmc(reg8);