soc/amd/common/block/pm: Add support for Modern Standby event logging

Log the GPE and PM1 wake events into the event log using the SMI handler
platform callback.

BUG=b:186792595, b:186800045
TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are
logged into the event logs.
5 | 2021-07-15 16:26:43 | S0ix Enter
6 | 2021-07-15 16:26:49 | S0ix Exit
7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22   <- Trackpad
8 | 2021-07-15 16:27:07 | S0ix Enter
9 | 2021-07-15 16:27:13 | S0ix Exit
10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0
25 | 2021-07-15 16:38:13 | S0ix Enter
26 | 2021-07-15 16:38:17 | S0ix Exit
27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint

Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-07-15 16:15:17 -06:00 committed by Werner Zeh
parent 589ac69850
commit b3af9f8d2e
3 changed files with 9 additions and 0 deletions

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@ -15,5 +15,6 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c
romstage-y += elog.c
ramstage-y += elog.c
smm-y += elog.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI

View File

@ -1,3 +1,4 @@
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c

View File

@ -4,6 +4,7 @@
#include <amdblocks/gpio_banks.h>
#include <amdblocks/pmlib.h>
#include <cbmem.h>
#include <elog.h>
#include <string.h>
static struct chipset_power_state chipset_state;
@ -14,6 +15,12 @@ void fill_chipset_state(void)
gpio_fill_wake_state(&chipset_state.gpio_state);
}
void elog_gsmi_cb_platform_log_wake_source(void)
{
fill_chipset_state();
acpi_log_events(&chipset_state);
}
static void add_chipset_state_cbmem(int unused)
{
struct chipset_power_state *state;