From b3b27f7dea3ac7170adfbfc7e6d4ca7bde9ab780 Mon Sep 17 00:00:00 2001 From: Robert Zieba Date: Mon, 3 Oct 2022 14:50:55 -0600 Subject: [PATCH] soc/amd/mendocino: Enable GPP clk req disabling for disabled devices Enable GPP clk req disabling for disabled PCIe devices. If a clk req line is enabled for a PCIe device that is not actually present and enabled then the L1SS could get confused and cause issues with suspending the SoC. BUG=b:250009974 TEST=Ran on skyrim proto device, verified that clk reqs are set appropriately Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248 Signed-off-by: Robert Zieba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/amd/chausie/Makefile.inc | 1 + src/mainboard/google/skyrim/Makefile.inc | 1 + src/soc/amd/mendocino/Kconfig | 1 + src/soc/amd/mendocino/chip.h | 7 ++----- src/soc/amd/mendocino/fch.c | 5 ++++- 5 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc index 2560886710..98b2cdd199 100644 --- a/src/mainboard/amd/chausie/Makefile.inc +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -8,6 +8,7 @@ romstage-y += port_descriptors.c ramstage-y += chromeos.c ramstage-y += gpio.c +ramstage-y += port_descriptors.c ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin),) APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FT6_Updatable.bin diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index 0fa733e293..c1d1108fc3 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -6,6 +6,7 @@ romstage-y += port_descriptors.c ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += port_descriptors.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d31b29dd43..9caee1eb5e 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -75,6 +75,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index 0e656f5d5a..04241ec288 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -92,11 +93,7 @@ struct soc_amd_mendocino_config { /* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ - enum { - GPP_CLK_ON, /* GPP clock always on; default */ - GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ - GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; + enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; /* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index e86cd318ce..5ebcc6b759 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -130,7 +131,7 @@ static void fch_init_acpi_ports(void) /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { - const struct soc_amd_mendocino_config *cfg = config_of_soc(); + struct soc_amd_mendocino_config *cfg = config_of_soc(); /* look-up table to be able to iterate over the PCIe clock output settings */ const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { @@ -145,6 +146,8 @@ static void gpp_clk_setup(void) uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); + pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], + ARRAY_SIZE(cfg->gpp_clk_config)); for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); /*