soc/amd/*: Hook up IOMMU ops in devicetree

This removed the need to maintain a PCI driver.

Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/cezanne/chipset.cb

@@ -5,7 +5,7 @@ chip soc/amd/cezanne
 	device domain 0 on
 		ops cezanne_pci_domain_ops
 		device pci 00.0 alias gnb on ops cezanne_root_complex_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 
 		device pci 01.0 on end # Dummy Host Bridge, do not disable
 		device pci 01.1 alias gpp_gfx_bridge_0 off end

src/soc/amd/common/block/iommu/iommu.c

@@ -2,7 +2,6 @@
 
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include <lib.h>
 
 static void iommu_read_resources(struct device *dev)
@@ -28,7 +27,7 @@ static const char *iommu_acpi_name(const struct device *dev)
 }
 #endif
 
-static struct device_operations iommu_ops = {
+struct device_operations amd_iommu_ops = {
 	.read_resources = iommu_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = pci_dev_enable_resources,
@@ -37,18 +36,3 @@ static struct device_operations iommu_ops = {
 	.acpi_name = iommu_acpi_name,
 #endif
 };
-
-static const unsigned short pci_device_ids[] = {
-	PCI_DID_AMD_15H_MODEL_303F_NB_IOMMU,
-	PCI_DID_AMD_15H_MODEL_707F_NB_IOMMU,
-	PCI_DID_AMD_17H_MODEL_1020_NB_IOMMU,
-	PCI_DID_AMD_17H_MODEL_606F_NB_IOMMU,
-	PCI_DID_AMD_17H_MODEL_A0AF_NB_IOMMU,
-	0
-};
-
-static const struct pci_driver iommu_driver __pci_driver = {
-	.ops = &iommu_ops,
-	.vendor = PCI_VID_AMD,
-	.devices = pci_device_ids,
-};

src/soc/amd/mendocino/chipset_mendocino.cb

@@ -5,7 +5,7 @@ chip soc/amd/mendocino
 	device domain 0 on
 		ops mendocino_pci_domain_ops
 		device pci 00.0 alias gnb on ops mendocino_root_complex_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 
 		device pci 01.0 on end # Dummy Host Bridge
 

src/soc/amd/mendocino/chipset_rembrandt.cb

@@ -5,7 +5,7 @@ chip soc/amd/mendocino
 	device domain 0 on
 		ops mendocino_pci_domain_ops
 		device pci 00.0 alias gnb on ops mendocino_root_complex_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 
 		device pci 01.0 on end # Dummy Host Bridge
 

src/soc/amd/morgana/chipset.cb

@@ -7,7 +7,7 @@ chip soc/amd/morgana
 	device domain 0 on
 		ops morgana_pci_domain_ops
 		device pci 00.0 alias gnb on ops morgana_root_complex_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 
 		device pci 01.0 on end # Dummy Host Bridge
 

src/soc/amd/picasso/chipset.cb

@@ -7,7 +7,7 @@ chip soc/amd/picasso
 	device domain 0 on
 		ops picasso_pci_domain_ops
 		device pci 00.0 alias gnb on ops picasso_root_complex_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 		device pci 01.0 on end # Dummy Host Bridge, do not disable
 		device pci 01.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
 		device pci 01.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end

src/soc/amd/stoneyridge/chipset_cz.cb

@@ -7,7 +7,7 @@ chip soc/amd/stoneyridge
 	device domain 0 on
 		ops stoneyridge_pci_domain_ops
 		device pci 00.0 alias gnb on ops stoneyridge_northbridge_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 		device pci 01.0 alias gfx off end # internal GPU
 		device pci 01.1 alias gfx_hda off end # display HD Audio controller
 		device pci 02.0 on end # Dummy Host Bridge, do not disable

src/soc/amd/stoneyridge/chipset_st.cb

@@ -7,7 +7,7 @@ chip soc/amd/stoneyridge
 	device domain 0 on
 		ops stoneyridge_pci_domain_ops
 		device pci 00.0 alias gnb on ops stoneyridge_northbridge_operations end
-		device pci 00.2 alias iommu off end
+		device pci 00.2 alias iommu off ops amd_iommu_ops end
 		device pci 01.0 alias gfx off end # internal GPU
 		device pci 01.1 alias gfx_hda off end # display HD Audio controller
 		device pci 02.0 on end # Dummy Host Bridge, do not disable