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mb/google/sarien/variants/arcada: Update thermal configuration for DPTF 

Update dptf for arcada DVT1.

BUG=b:123924662
TEST=Built and tested on arcada system

Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Change-Id: Ia8024a69547a569d288e02931190a98676eeaab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Mike Hsieh 2019-05-02 14:43:26 +08:00 committed by Duncan Laurie
parent 49df54a1dc
commit b3ddb29c36
1 changed files with 10 additions and 10 deletions
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20
src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl
View File

@ -13,14 +13,14 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#define DPTF_CPU_PASSIVE 96 #define DPTF_CPU_PASSIVE 90
#define DPTF_CPU_CRITICAL 103 #define DPTF_CPU_CRITICAL 105
/* Skin Sensor for CPU VR temperature monitor */ /* Skin Sensor for CPU VR temperature monitor */
#define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_NAME "Skin" #define DPTF_TSR0_SENSOR_NAME "Skin"
#define DPTF_TSR0_PASSIVE 56 #define DPTF_TSR0_PASSIVE 60
#define DPTF_TSR0_CRITICAL 108 #define DPTF_TSR0_CRITICAL 105
/* Memory Sensor for DDR temperature monitor */ /* Memory Sensor for DDR temperature monitor */
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_ID 2
@ -31,24 +31,24 @@
/* M.2 Sensor for Ambient temperature monitor */ /* M.2 Sensor for Ambient temperature monitor */
#define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "Ambient" #define DPTF_TSR2_SENSOR_NAME "Ambient"
#define DPTF_TSR2_PASSIVE 50 #define DPTF_TSR2_PASSIVE 37
#define DPTF_TSR2_CRITICAL 95 #define DPTF_TSR2_CRITICAL 80
#undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_FAN_CONTROL
#undef DPTF_ENABLE_CHARGER #undef DPTF_ENABLE_CHARGER
Name (DTRT, Package () { Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 },
/* CPU Throttle Effect on Skin (TSR0) */ /* CPU Throttle Effect on Skin (TSR0) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 500, 30, 0, 0, 0, 0 },
/* CPU Throttle Effect on DDR (TSR1) */ /* CPU Throttle Effect on DDR (TSR1) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 90, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 50, 2, 0, 0, 0 },
/* CPU Throttle Effect on Ambient (TSR2) */ /* CPU Throttle Effect on Ambient (TSR2) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()