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soc/intel/tigerlake: configure ethernet

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Configure ethernet based on board config

BUG=none
BRANCH=none
TEST= build TGLRVP and check ethernet is disabled based on devicetree

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-02-27 15:54:56 -08:00 committed by Patrick Georgi
parent d615230cce
commit b3fa6a03a8
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/tigerlake/fsp_params_tgl.c
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@ -135,6 +135,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsDevSlp));
}
/* LAN */
dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
if (!dev)
params->PchLanEnable = 0;
else
params->PchLanEnable = dev->enabled;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;