mb/google/brya/var/banshee: Update thermal settings PL1 and PL2

Update PL1 and PL2 based on the suggestion of the thermal team.
Then the settings are both updated in firmware log.

BUG=b:233703656, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/mainboard/google/brya/variants/banshee/Makefile.inc

@@ -3,4 +3,5 @@ bootblock-y += gpio.c
 romstage-y += memory.c
 romstage-y += gpio.c
 ramstage-y += gpio.c
+ramstage-y += ramstage.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c

src/mainboard/google/brya/variants/banshee/overridetree.cb

@@ -68,6 +68,12 @@ chip soc/intel/alderlake
 
 	register "tcc_offset" = "10"     # TCC of 90
 
+	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
+		.tdp_pl1_override = 30,
+		.tdp_pl2_override = 60,
+		.tdp_pl4 = 90,
+	}"
+
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf

src/mainboard/google/brya/variants/banshee/ramstage.c

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <device/pci_ids.h>
+
+const struct cpu_power_limits limits[] = {
+	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */
+	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 5000, 30000, 60000, 60000, 90000 },
+};
+
+void variant_devtree_update(void)
+{
+	size_t total_entries = ARRAY_SIZE(limits);
+	variant_update_power_limits(limits, total_entries);
+}