diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 97bb69142d..1411a7c13d 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/apollolake
 	# route, i.e., if this route changes then the affected GPE
 	# offset bits also need to be changed. This sets the PMC register
 	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+	register "gpe0_dw1" = "PMC_GPE_N_63_32"
 	register "gpe0_dw2" = "PMC_GPE_N_95_64"
 	register "gpe0_dw3" = "PMC_GPE_NW_31_0"
 
@@ -117,6 +117,7 @@ chip soc/intel/apollolake
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 on
 			chip drivers/intel/wifi
+				register "wake" = "GPE0_DW1_11"
 				device pci 00.0 on end
 			end
 		end	# - PCIe-A 0 Onboard M2 Slot(Wifi)
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
index f839850a99..c7d8d3d0e4 100644
--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -166,8 +166,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */
 	PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */
-	//TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */
+	PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */
 
 	/* PCIE_CLKREQ[0:3]_B */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/
diff --git a/src/mainboard/google/octopus/variants/bip/devicetree.cb b/src/mainboard/google/octopus/variants/bip/devicetree.cb
index 7520110ca7..277cb764f0 100644
--- a/src/mainboard/google/octopus/variants/bip/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/bip/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/apollolake
 	# route, i.e., if this route changes then the affected GPE
 	# offset bits also need to be changed. This sets the PMC register
 	# GPE_CFG fields.
-	register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+	register "gpe0_dw1" = "PMC_GPE_N_63_32"
 	register "gpe0_dw2" = "PMC_GPE_N_95_64"
 	register "gpe0_dw3" = "PMC_GPE_NW_31_0"
 
@@ -117,6 +117,7 @@ chip soc/intel/apollolake
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 on
 			chip drivers/intel/wifi
+				register "wake" = "GPE0_DW1_11"
 				device pci 00.0 on end
 			end
 		end	# - PCIe-A 0 Onboard M2 Slot(Wifi)
diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c
index e809ca2c61..d7396cac4b 100644
--- a/src/mainboard/google/octopus/variants/bip/gpio.c
+++ b/src/mainboard/google/octopus/variants/bip/gpio.c
@@ -164,8 +164,7 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPO(GPIO_116, 1, DEEP), /* WIFI_DISABLE_L */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE1_B */
 	PAD_CFG_GPIO_HI_Z(GPIO_118, NONE, DEEP, HIZCRx0, DISPUPD),/* PCIE_WAKE2_B -- unused */
-	//TODO Reef uses PCIE_WAKE0 as GPI_SCI. Whats the difference?
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PCIE_WAKE3_B */
+	PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */
 
 	/* PCIE_CLKREQ[0:3]_B */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/