From b433470b02e773c182adffde654d3fcbb2b9f9b5 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sun, 11 Dec 2022 10:08:34 +0100 Subject: [PATCH] soc/cavium/cn81xx: Use write{32,64}p() Change-Id: I9c94f45264f541ce0849a53245534a10aaa5d854 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/70576 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/cavium/cn81xx/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/cavium/cn81xx/cpu.c b/src/soc/cavium/cn81xx/cpu.c index 14aff58a2a..43b64d5430 100644 --- a/src/soc/cavium/cn81xx/cpu.c +++ b/src/soc/cavium/cn81xx/cpu.c @@ -72,7 +72,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) return 1; /* Write the address of the main entry point */ - write64((void *)MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init); + write64p(MIO_BOOT_AP_JUMP, (uintptr_t)secondary_init); /* Get coremask of cores in reset */ const uint64_t reset = read64p(RST_PP_RESET); @@ -86,7 +86,7 @@ size_t start_cpu(size_t cpu, void (*entry_64)(size_t core_id)) printk(BIOS_DEBUG, "CPU: Taking core %zu out of reset.\n", cpu); /* Release core from reset */ - write64((void *)RST_PP_RESET, reset & ~coremask); + write64p(RST_PP_RESET, reset & ~coremask); /* Wait for cores to finish coming out of reset */ udelay(1);