mb/system76/oryp8: Add System76 Oryx Pro 8
https://tech-docs.system76.com/models/oryp8/README.html Tested with TianoCore (UeifPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone & microphone jack - Combined 3.5mm microphone & S/PDIF jack* - S3 suspend/resume - Booting to Pop!_OS Linux 21.10 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Jeremy Soller
Patrick Georgi
parent
fdaccd875d
commit
b44202b29a
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@ -193,6 +193,7 @@ The boards in this section are not real mainboards, but emulators.
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- [Oryx Pro 5](system76/oryp5.md)
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- [Oryx Pro 6](system76/oryp6.md)
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- [Oryx Pro 7](system76/oryp7.md)
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- [Oryx Pro 8](system76/oryp8.md)
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## Texas Instruments
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@ -0,0 +1,70 @@
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# System76 Oryx Pro 8 (oryp8)
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## Specs
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- CPU
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- Intel Core i7-11800H
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- Chipset
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- Intel HM570
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- EC
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- ITE IT570E running [System76 EC](https://github.com/system76/ec)
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- Graphics
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- dGPU options
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- NVIDIA GeForce RTX 3070 (Max-Q)
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- NVIDIA GeForce RTX 3080 (Max-Q)
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- eDP options
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- 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
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- 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
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- 1x HDMI 2.1
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- 1x Mini DisplayPort 1.4
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- 1x DisplayPort 1.4 over USB-C
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- Memory
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- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
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- Networking
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- Gigabit Ethernet
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- M.2 PCIe/CNVi WiFi/Bluetooth
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- Intel Wi-Fi 6 AX200/AX201
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- Power
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- 180W (19.5V, 9.23A) AC barrel adapter
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- Lite-On PA-1181-16, using a C5 power cord
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- 73Wh 3-cell battery
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- Sound
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- Realtek ALC1220 codec
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- TI TAS5825M smart amp
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- Internal speakers and microphone
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- Combined 3.5mm headphone & microphone jack
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- Combined 3.5mm microphone & S/PDIF jack
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- HDMI, mDP, USB-C DP audio
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- Storage
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- 1x M.2 PCIe NVMe Gen 4 SSD
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- 1x M.2 PCIe NVMe Gen 3 or SATA SSD
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- USB
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- 1x USB Type-C with Thunderbolt 4
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- 3x USB 3.0 Type-A
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- Dimensions
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- 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
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- 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
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## Flashing coreboot
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```eval_rst
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+---------------------+-----------------+
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| Type | Value |
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+=====================+=================+
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| Socketed flash | no |
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+---------------------+-----------------+
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| Vendor | GigaDevice |
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+---------------------+-----------------+
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| Model | GD25B127D |
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+---------------------+-----------------+
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| Size | 16 MiB |
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+---------------------+-----------------+
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| Package | SOIC-8 |
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+---------------------+-----------------+
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| Internal flashing | yes |
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+---------------------+-----------------+
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| External flashing | yes |
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+---------------------+-----------------+
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```
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The flash chip (U74) is right of the bottom DIMM slot.
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@ -0,0 +1,66 @@
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if BOARD_SYSTEM76_ORYP8
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_HID
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select DRIVERS_I2C_TAS5825M
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select EC_SYSTEM76_EC_COLOR_KEYBOARD
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_GMA_HAVE_VBT
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select INTEL_LPSS_UART_FOR_CONSOLE
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM2
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select NO_UART_ON_SUPERIO
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select PCIEXP_HOTPLUG
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select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
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select SOC_INTEL_TIGERLAKE
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select SOC_INTEL_TIGERLAKE_PCH_H
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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select TPM_RDRESP_NEED_DELAY
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config MAINBOARD_DIR
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default "system76/oryp8"
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config MAINBOARD_PART_NUMBER
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default "oryp8"
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Oryx Pro"
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config MAINBOARD_VERSION
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default "oryp8"
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config CBFS_SIZE
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default 0xA00000
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config CONSOLE_POST
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default y
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config DIMM_MAX
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default 4
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config DIMM_SPD_SIZE
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default 512
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config ONBOARD_VGA_IS_PRIMARY
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default y
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config POST_DEVICE
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default n
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config UART_FOR_CONSOLE
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default 2
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# PM Timer Disabled, saves power
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config USE_PM_ACPI_TIMER
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default n
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endif
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@ -0,0 +1,2 @@
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config BOARD_SYSTEM76_ORYP8
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bool "oryp8"
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@ -0,0 +1,13 @@
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## SPDX-License-Identifier: GPL-2.0-only
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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bootblock-y += bootblock.c
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bootblock-y += gpio_early.c
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romstage-y += romstage.c
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ramstage-y += gpio.c
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ramstage-y += hda_verb.c
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ramstage-y += ramstage.c
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ramstage-y += tas5825m.c
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6B
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#include <ec/system76/ec/acpi/ec.asl>
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Scope (\_SB) {
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#include "sleep.asl"
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}
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <intelblocks/gpio.h>
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Method (PGPM, 1, Serialized)
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{
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For (Local0 = 0, Local0 < 6, Local0++)
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{
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\_SB.PCI0.CGPM (Local0, Arg0)
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}
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}
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/*
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* Method called from _PTS prior to system sleep state entry
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* Enables dynamic clock gating for all 5 GPIO communities
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*/
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Method (MPTS, 1, Serialized)
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{
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\_SB.PCI0.LPCB.EC0.PTS (Arg0)
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PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
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}
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/*
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* Method called from _WAK prior to system sleep state wakeup
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* Disables dynamic clock gating for all 5 GPIO communities
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*/
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Method (MWAK, 1, Serialized)
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{
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PGPM (0)
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\_SB.PCI0.LPCB.EC0.WAK (Arg0)
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}
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/*
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* S0ix Entry/Exit Notifications
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* Called from \_SB.PEPD._DSM
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*/
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Method (MS0X, 1, Serialized)
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{
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If (Arg0 == 1) {
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/* S0ix Entry */
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PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
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} Else {
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/* S0ix Exit */
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PGPM (0)
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}
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}
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@ -0,0 +1,8 @@
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Vendor name: System76
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Board name: oryp8
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Category: laptop
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Release year: 2021
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <mainboard/gpio.h>
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void bootblock_mainboard_init(void)
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{
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mainboard_configure_early_gpios();
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}
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@ -0,0 +1,2 @@
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boot_option=Fallback
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debug_level=Debug
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@ -0,0 +1,34 @@
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# SPDX-License-Identifier: GPL-2.0-only
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entries
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0 384 r 0 reserved_memory
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# RTC_CLK_ALTCENTURY
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400 8 r 0 century
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412 4 e 6 debug_level
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984 16 h 0 check_sum
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enumerations
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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checksums
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checksum 408 983 984
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Binary file not shown.
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@ -0,0 +1,221 @@
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chip soc/intel/tigerlake
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register "common_soc_config" = "{
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// Touchpad I2C bus
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 80,
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.fall_time_ns = 110,
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},
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}"
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# ACPI (soc/intel/tigerlake/acpi.c)
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# CPU (soc/intel/tigerlake/cpu.c)
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# Power limits
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register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
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.tdp_pl1_override = 45,
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.tdp_pl2_override = 90,
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}"
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register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
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.tdp_pl1_override = 45,
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.tdp_pl2_override = 90,
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}"
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# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
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# Enable C6 DRAM
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register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
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# Acoustic settings
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register "AcousticNoiseMitigation" = "1"
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register "SlowSlewRate" = "SLEW_FAST_8"
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register "FastPkgCRampDisable" = "1"
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# FIVR configuration
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# Read EXT_RAIL_CONFIG to determine bitmaps
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# sudo devmem2 0xfe0011b8
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# 0x0
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# Read EXT_V1P05_VR_CONFIG
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# sudo devmem2 0xfe0011c0
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# 0x1a42000
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# Read EXT_VNN_VR_CONFIG0
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# sudo devmem2 0xfe0011c4
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# 0x1a42000
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# TODO: v1p05 voltage and vnn icc max?
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = 0,
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.vnn_enable_bitmap = 0,
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.v1p05_supported_voltage_bitmap = 0,
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.vnn_supported_voltage_bitmap = 0,
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.v1p05_icc_max_ma = 500,
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.vnn_sx_voltage_mv = 1050,
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}"
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# Read LPM_EN, make sure to invert the bits
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# sudo devmem2 0xfe001c78
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# 0x9
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register "LpmStateDisableMask" = "
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LPM_S0i2_1 |
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LPM_S0i2_2 |
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LPM_S0i3_1 |
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LPM_S0i3_2 |
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LPM_S0i3_3 |
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LPM_S0i3_4
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"
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# Thermal
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register "tcc_offset" = "10"
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# Enable CNVi BT
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register "CnviBtCore" = "true"
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# PM Util (soc/intel/tigerlake/pmutil.c)
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# GPE configuration
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register "pmc_gpe0_dw0" = "PMC_GPP_R"
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register "pmc_gpe0_dw1" = "PMC_GPP_B"
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register "pmc_gpe0_dw2" = "PMC_GPP_D"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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subsystemid 0x1558 0x65f1 inherit
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#From CPU EDS(575683)
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device ref system_agent on end
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device ref peg1 on
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# PCIe PEG1 x16, Clock 9 (DGPU)
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register "PcieClkSrcUsage[9]" = "0x41"
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register "PcieClkSrcClkReq[9]" = "9"
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
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register "enable_delay_ms" = "16"
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register "enable_off_delay_ms" = "4"
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register "reset_delay_ms" = "10"
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register "reset_off_delay_ms" = "4"
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# TODO: Support disable/enable CPU RP clock
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register "srcclk_pin" = "-1" # PEG_CLKREQ#
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device generic 0 on end
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end
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end
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device ref igpu on
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# DDIA is eDP
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register "DdiPortAConfig" = "1"
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "0"
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end
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device ref dptf on
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register "Device4Enable" = "1"
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end
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device ref peg0 on
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# PCIe PEG0 x4, Clock 7 (SSD1)
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register "PcieClkSrcUsage[7]" = "0x40"
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register "PcieClkSrcClkReq[7]" = "7"
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end
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device ref tbt_pcie_rp0 on end # TYPEC1
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device ref gna on end
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device ref north_xhci on # TYPEC1
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register "TcssXhciEn" = "1"
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end
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device ref tbt_dma0 on end # TYPEC1
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# From PCH EDS(615985)
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device ref south_xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
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register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
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register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
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end
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device ref shared_ram on end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
|
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end
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end
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device ref i2c0 on
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# Touchpad I2C bus
|
||||
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
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chip drivers/i2c/hid
|
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register "generic.hid" = ""SYNA1202""
|
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register "generic.desc" = ""Synaptics Touchpad""
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register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
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register "generic.probed" = "1"
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register "hid_desc_reg_offset" = "0x20"
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device i2c 2c on end
|
||||
end
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end
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device ref heci1 on end
|
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device ref uart2 on
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# Debug console
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register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
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end
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device ref sata on
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register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
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||||
end
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||||
device ref pcie_rp5 on
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# PCIe root port #5 x1, Clock 8 (GLAN)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
register "PcieClkSrcUsage[8]" = "4"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# PCIe root port #6 x1, Clock 10 (CARD)
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
register "PcieClkSrcUsage[10]" = "5"
|
||||
register "PcieClkSrcClkReq[10]" = "10"
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# PCIe root port #8 x1, Clock 2 (WLAN)
|
||||
register "PcieRpEnable[7]" = "1"
|
||||
register "PcieRpLtrEnable[7]" = "1"
|
||||
register "PcieClkSrcUsage[2]" = "7"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# PCIe root port #9 x4, Clock 6 (SSD2)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[6]" = "8"
|
||||
register "PcieClkSrcClkReq[6]" = "6"
|
||||
end
|
||||
device ref pch_espi on
|
||||
register "gen1_dec" = "0x00040069" # EC PM channel
|
||||
register "gen2_dec" = "0x00fc0E01" # AP/EC command
|
||||
register "gen3_dec" = "0x00fc0F01" # AP/EC debug
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device ref p2sb on end
|
||||
device ref pmc hidden end
|
||||
device ref hda on
|
||||
register "PchHdaAudioLinkHdaEnable" = "1"
|
||||
end
|
||||
device ref smbus on
|
||||
register "SmbusEnable" = "1"
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end
|
||||
end
|
||||
device ref fast_spi on end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
ACPI_DSDT_REV_2,
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725
|
||||
)
|
||||
{
|
||||
#include <acpi/dsdt_top.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0)
|
||||
{
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/southbridge.asl>
|
||||
#include <soc/intel/tigerlake/acpi/tcss.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* ------- GPIO Group GPD ------- */
|
||||
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
|
||||
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
|
||||
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
|
||||
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
|
||||
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
|
||||
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
|
||||
PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7
|
||||
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
|
||||
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
|
||||
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
|
||||
PAD_NC(GPD11, NONE),
|
||||
PAD_NC(GPD12, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_A ------- */
|
||||
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
|
||||
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
|
||||
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
|
||||
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
|
||||
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS#_EC
|
||||
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
|
||||
PAD_NC(GPP_A7, NONE),
|
||||
PAD_NC(GPP_A8, NONE),
|
||||
PAD_NC(GPP_A9, NONE),
|
||||
PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // SERIRQ_ESPI_ALERT0
|
||||
PAD_NC(GPP_A11, NONE),
|
||||
PAD_NC(GPP_A12, NONE),
|
||||
PAD_NC(GPP_A13, NONE),
|
||||
PAD_NC(GPP_A14, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_B ------- */
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ#
|
||||
PAD_CFG_GPI(GPP_B1, NONE, DEEP), // VRALERT#_PD
|
||||
PAD_CFG_GPI(GPP_B2, NONE, DEEP),
|
||||
PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
|
||||
PAD_NC(GPP_B4, NONE),
|
||||
PAD_NC(GPP_B5, NONE),
|
||||
PAD_NC(GPP_B6, NONE),
|
||||
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ2#
|
||||
PAD_NC(GPP_B8, NONE),
|
||||
PAD_NC(GPP_B9, NONE),
|
||||
PAD_NC(GPP_B10, NONE),
|
||||
PAD_NC(GPP_B11, NONE),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
|
||||
PAD_CFG_GPO(GPP_B15, 1, DEEP), // SATA_M2_PWR_EN1
|
||||
PAD_NC(GPP_B16, NONE),
|
||||
PAD_NC(GPP_B17, NONE),
|
||||
PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
|
||||
PAD_NC(GPP_B19, NONE),
|
||||
PAD_NC(GPP_B20, NONE),
|
||||
PAD_NC(GPP_B21, NONE),
|
||||
PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT strap
|
||||
PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC clock
|
||||
|
||||
/* ------- GPIO Group GPP_C ------- */
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT
|
||||
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE#
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // PCH_I2C_SDA
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // PCH_I2C_SCL
|
||||
PAD_CFG_GPI(GPP_C5, NONE, DEEP), // eSPI/LPC select strap
|
||||
PAD_CFG_GPI(GPP_C6, NONE, DEEP), // SCI#
|
||||
PAD_CFG_GPI(GPP_C7, NONE, DEEP), // SWI#
|
||||
PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1
|
||||
PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2
|
||||
PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3
|
||||
PAD_CFG_GPI(GPP_C12, NONE, DEEP), // BOARD_ID4
|
||||
PAD_NC(GPP_C13, NONE),
|
||||
PAD_CFG_GPI(GPP_C14, NONE, DEEP), // GPP_C14_RTD3
|
||||
PAD_NC(GPP_C15, NONE),
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // I2C_SDA_Pantone
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // I2C_SCL_Pantone
|
||||
//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN
|
||||
PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI#
|
||||
|
||||
/* ------- GPIO Group GPP_D ------- */
|
||||
PAD_NC(GPP_D0, NONE),
|
||||
PAD_NC(GPP_D1, NONE),
|
||||
PAD_NC(GPP_D2, NONE),
|
||||
PAD_NC(GPP_D3, NONE),
|
||||
PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1CLK
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST#
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
|
||||
PAD_NC(GPP_D7, NONE),
|
||||
PAD_NC(GPP_D8, NONE),
|
||||
PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_CLK
|
||||
PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_DATA
|
||||
PAD_NC(GPP_D11, NONE),
|
||||
PAD_NC(GPP_D12, NONE),
|
||||
PAD_NC(GPP_D13, NONE),
|
||||
PAD_NC(GPP_D14, NONE),
|
||||
PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1_DATA
|
||||
PAD_NC(GPP_D16, NONE),
|
||||
PAD_NC(GPP_D17, NONE),
|
||||
PAD_NC(GPP_D18, NONE),
|
||||
PAD_NC(GPP_D19, NONE),
|
||||
PAD_NC(GPP_D20, NONE),
|
||||
PAD_NC(GPP_D21, NONE),
|
||||
PAD_NC(GPP_D22, NONE),
|
||||
PAD_CFG_GPO(GPP_D23, 1, DEEP), // GPU_EVENT#
|
||||
|
||||
/* ------- GPIO Group GPP_E ------- */
|
||||
PAD_NC(GPP_E0, NONE),
|
||||
PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // M.2_SSD1_PEDET
|
||||
PAD_NC(GPP_E2, NONE),
|
||||
PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
|
||||
PAD_NC(GPP_E4, NONE),
|
||||
PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), // M2_P1_SATA_DEVSLP
|
||||
PAD_NC(GPP_E6, NONE),
|
||||
PAD_NC(GPP_E7, NONE),
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
|
||||
PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
|
||||
PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
|
||||
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
|
||||
|
||||
/* ------- GPIO Group GPP_F ------- */
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPO(GPP_F1, 1, DEEP), // LAN_PLT_RST#
|
||||
PAD_CFG_GPO(GPP_F2, 1, PLTRST), // GPIO_LANRTD3
|
||||
PAD_CFG_GPO(GPP_F3, 0, PLTRST), // GPP_F3_TBT_FORCE_PWR
|
||||
PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPO(GPP_F6, 1, DEEP), // GPIO_LAN_EN
|
||||
PAD_CFG_GPO(GPP_F7, 0, DEEP), // PCH_GPIO_PK_MUTE
|
||||
//PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
|
||||
//PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
|
||||
PAD_NC(GPP_F11, NONE),
|
||||
PAD_NC(GPP_F12, NONE),
|
||||
PAD_NC(GPP_F13, NONE),
|
||||
PAD_NC(GPP_F14, NONE),
|
||||
PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
|
||||
PAD_NC(GPP_F16, NONE),
|
||||
PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON
|
||||
PAD_CFG_GPO(GPP_F18, 1, DEEP), // EAPD_MODE
|
||||
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
|
||||
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
|
||||
PAD_NC(GPP_F22, NONE), // PCH_VNN_CTRL
|
||||
PAD_CFG_GPO(GPP_F23, 1, PLTRST), // CARD_RTD3_RST#
|
||||
|
||||
/* ------- GPIO Group GPP_G ------- */
|
||||
PAD_NC(GPP_G0, NONE),
|
||||
PAD_NC(GPP_G1, NONE),
|
||||
PAD_NC(GPP_G2, NONE),
|
||||
PAD_NC(GPP_G3, NONE),
|
||||
PAD_NC(GPP_G4, NONE),
|
||||
PAD_NC(GPP_G5, NONE),
|
||||
PAD_CFG_GPO(GPP_G6, 1, DEEP), // GPIO_CARD_AUX
|
||||
PAD_CFG_GPO(GPP_G7, 1, DEEP), // GPIO_CARD
|
||||
PAD_NC(GPP_G8, NONE),
|
||||
PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9
|
||||
PAD_NC(GPP_G10, NONE),
|
||||
PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11
|
||||
PAD_NC(GPP_G12, NATIVE), // GPP_G12_TBT_LSX_TXD
|
||||
PAD_NC(GPP_G13, NATIVE), // GPP_G13_TBT_LSX0_RXD
|
||||
PAD_NC(GPP_G14, NONE),
|
||||
PAD_CFG_GPI(GPP_G15, NONE, DEEP), // GPP_G15
|
||||
|
||||
/* ------- GPIO Group GPP_H ------- */
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // SSD_CLKREQ6#
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SDD_PEX4_CLKREQ7#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // LAN_CLKREQ8#
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // PEG_CLKREQ9#
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // CARD_CLKREQ10#
|
||||
PAD_NC(GPP_H5, NONE),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST#
|
||||
PAD_NC(GPP_H7, NONE),
|
||||
PAD_NC(GPP_H8, NONE),
|
||||
PAD_NC(GPP_H9, NONE),
|
||||
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // SML2CLK
|
||||
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // SML2DATA
|
||||
PAD_CFG_GPI(GPP_H12, NONE, DEEP), // GPP_H12
|
||||
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML3CLK
|
||||
PAD_CFG_GPI(GPP_H14, NONE, DEEP), // SML3DATA
|
||||
PAD_CFG_GPI(GPP_H15, NONE, PLTRST), // SML3ALERT#
|
||||
PAD_CFG_GPI(GPP_H16, NONE, DEEP), // SML4CLK
|
||||
PAD_CFG_GPO(GPP_H17, 1, DEEP), // SATA_M2_PWR_EN2
|
||||
PAD_CFG_GPI(GPP_H18, NONE, DEEP), // GPP_H18
|
||||
PAD_NC(GPP_H19, NONE),
|
||||
PAD_NC(GPP_H20, NONE),
|
||||
PAD_NC(GPP_H21, NONE),
|
||||
PAD_NC(GPP_H22, NONE),
|
||||
PAD_CFG_GPO(GPP_H23, 1, DEEP), // GPP_H23_SDD1_RST#
|
||||
|
||||
/* ------- GPIO Group GPP_I ------- */
|
||||
PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // G_DP_DHPD_E
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // HDMI_HPD
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46880100, 0x0000), // CPU_DPIP0_HPD
|
||||
PAD_NC(GPP_I4, NONE),
|
||||
PAD_NC(GPP_I5, NONE),
|
||||
PAD_NC(GPP_I6, NONE),
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_NC(GPP_I8, NONE),
|
||||
PAD_CFG_GPO(GPP_I9, 1, DEEP), // GGPP_I9_SDD2_RST#
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, PLTRST), // USB_OC4#
|
||||
PAD_CFG_GPI(GPP_I12, NONE, PLTRST), // USB_OC5#
|
||||
PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6#
|
||||
PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7#
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // GPP_J1
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_NVDD_EN
|
||||
PAD_NC(GPP_J9, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_CFG_GPO(GPP_K0, 0, DEEP), // OVRM
|
||||
PAD_NC(GPP_K1, NONE),
|
||||
PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R
|
||||
PAD_NC(GPP_K3, NONE),
|
||||
PAD_NC(GPP_K4, NONE),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // SB_IEDP_HPD
|
||||
PAD_NC(GPP_K7, NONE),
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
|
||||
PAD_NC(GPP_K10, NONE),
|
||||
PAD_CFG_GPI(GPP_K11, NONE, PLTRST), // GC6_FB_EN_PCH
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP), // CHIP_ID1
|
||||
PAD_CFG_GPI(GPP_R9, NONE, DEEP), // GSYNC_DET
|
||||
PAD_CFG_GPI(GPP_R10, NONE, DEEP), // DDS_DET
|
||||
PAD_CFG_GPI(GPP_R11, NONE, DEEP), // CHIP_ID0
|
||||
PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN#
|
||||
PAD_NC(GPP_R13, NONE),
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
PAD_CFG_GPI(GPP_R16, NONE, DEEP), // BL_PWM_EN_EC
|
||||
PAD_CFG_GPI(GPP_R17, NONE, DEEP), // PLVDD_RST_EC
|
||||
PAD_CFG_GPI(GPP_R18, NONE, DEEP), // MUX_CTRL_BIOS
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP), // PS8461_SW
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_CFG_GPI(GPP_S6, NONE, DEEP), // DMIC_CLK0
|
||||
PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DATA0
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155865f1, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155865f1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Enable DMIC microphone on ALC1220
|
||||
0x02050036,
|
||||
0x02042a6a,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
void mainboard_configure_early_gpios(void);
|
||||
void mainboard_configure_gpios(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/ramstage.h>
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
|
||||
{
|
||||
// PEG0 Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[0] = 0;
|
||||
params->CpuPcieRpLtrEnable[0] = 1;
|
||||
params->CpuPcieRpPtmEnabled[0] = 0;
|
||||
|
||||
// PEG1 Config
|
||||
params->CpuPcieRpAdvancedErrorReporting[1] = 0;
|
||||
params->CpuPcieRpLtrEnable[1] = 1;
|
||||
params->CpuPcieRpPtmEnabled[1] = 0;
|
||||
|
||||
// IOM config
|
||||
params->PchUsbOverCurrentEnable = 0;
|
||||
params->PortResetMessageEnable[8] = 1; // TYPEC1
|
||||
params->UsbTcPortEn = 1;
|
||||
|
||||
// Low latency legacy I/O
|
||||
params->PchLegacyIoLowLatency = 1;
|
||||
|
||||
mainboard_configure_gpios();
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <fsp/util.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR4,
|
||||
.ddr4_config = {
|
||||
.dq_pins_interleaved = true,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const bool half_populated = false;
|
||||
|
||||
// Enable M.2 PCIE 4.0 and PEG1
|
||||
mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
|
||||
|
||||
memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue