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mb/intel/tglrvp: Add support of TPM over SPI 

Bug=none
Test=emerge build and boot on tglrvp and check that
tpm is probed successfully from coreboot.

Cq-Depend:chromium-review:1881839
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
This commit is contained in:
Shaunak Saha 2020-08-23 21:35:21 -07:00 committed by Patrick Georgi
parent 726282b44f
commit b449b9c182
5 changed files with 65 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/mainboard/intel/tglrvp/Kconfig
View File

@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS
select PCIEXP_HOTPLUG
select HAVE_SPD_IN_CBFS
select SOC_INTEL_CSE_LITE_SKU
select MAINBOARD_HAS_TPM2
select MAINBOARD_HAS_SPI_TPM_CR50
select SPI_TPM
config CHROMEOS
bool
@ -102,9 +105,16 @@ endchoice
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA
config UART_FOR_CONSOLE
int
default 2
config DRIVER_TPM_SPI_BUS
default 0x2
config TPM_TIS_ACPI_INTERRUPT
int
default 54 # GPE0_DW1_22 (GPP_C22)
endif

23
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -9,8 +9,8 @@ chip soc/intel/tigerlake
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_D"
# Enable heci1 communication
register "HeciEnabled" = "1"
@ -86,14 +86,14 @@ chip soc/intel/tigerlake
register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
}"
register "SerialIoGSpiCsMode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI1] = 1,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
@ -152,6 +152,10 @@ chip soc/intel/tigerlake
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
@ -294,8 +298,15 @@ chip soc/intel/tigerlake
device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9
device pci 1e.2 off end # GSPI0 0xA0AA
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1e.2 on end # GSPI0 0xA0AA
device pci 1e.3 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)"
device spi 0 on end
end
end # GSPI1 0xA0AB
device pci 1f.0 on
chip ec/google/chromeec
device pnp 0c09.0 on end

10
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
View File

@ -94,6 +94,16 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
/* TPM */
/* B19 : GSPI1_CS0B */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK */
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* B21 : GSPI1_MISO */
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B22 : GSPI1_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
};
const struct pad_config *variant_gpio_table(size_t *num)

23
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -9,8 +9,8 @@ chip soc/intel/tigerlake
# route. i.e. If this route changes then the affected GPE
# offset bits also need to be changed.
register "pmc_gpe0_dw0" = "GPP_B"
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_D"
# Enable heci1 communication
register "HeciEnabled" = "1"
@ -90,14 +90,14 @@ chip soc/intel/tigerlake
register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI1] = PchSerialIoPci,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
}"
register "SerialIoGSpiCsMode" = "{
[PchSerialIoIndexGSPI0] = 0,
[PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI1] = 1,
[PchSerialIoIndexGSPI2] = 0,
[PchSerialIoIndexGSPI3] = 0,
}"
@ -156,6 +156,10 @@ chip soc/intel/tigerlake
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.gspi[1] = {
.speed_mhz = 1,
.early_init = 1,
},
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
@ -298,8 +302,15 @@ chip soc/intel/tigerlake
device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9
device pci 1e.2 off end # GSPI0 0xA0AA
device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1e.2 on end # GSPI0 0xA0AA
device pci 1e.3 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C22_IRQ)"
device spi 0 on end
end
end # GSPI1 0xA0AB
device pci 1f.0 on
chip ec/google/chromeec
device pnp 0c09.0 on end

10
src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
View File

@ -90,6 +90,16 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* HPD_1 */
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDP_1_CTRCLK */
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDP_1_CTRDATA */
/* TPM */
/* B19 : GSPI1_CS0B */
PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* B20 : GSPI1_CLK */
PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* B21 : GSPI1_MISO */
PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* B22 : GSPI1_MOSI */
PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
};
const struct pad_config *variant_gpio_table(size_t *num)