From b46ec389bd5606327b72142a4a1dcf5d3a271381 Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Thu, 8 Apr 2021 18:11:01 -0700 Subject: [PATCH] mb/intel/adlrvp_m: Add UART0 GPIO config for ADL-M RVP This patch adds UART0 config in early GPIO table Branch=None Test=Build coreboot and boot on ADLRVP-M board. Check UART logs Signed-off-by: Anil Kumar Change-Id: Ic0cc955a02936b74f44fed55a9f4b8054646681a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52201 Reviewed-by: Bora Guvendik Reviewed-by: Bernardo Perez Priego Reviewed-by: Varshit B Pandya Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/early_gpio_m.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index c2570045eb..116d3c6840 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -13,7 +13,17 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A8, 1, DEEP), }; +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 RX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* UART0 TX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + void variant_configure_early_gpio_pads(void) { + if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); }