mb/google: Use chromeec_smi_sleep()

Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Kyösti Mälkki 2023-01-05 18:12:57 +02:00
parent d84ace50e3
commit b470624c74
3 changed files with 3 additions and 57 deletions

View File

@ -5,7 +5,6 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <soc/pm.h>
#include <soc/gpio.h>
@ -52,24 +51,7 @@ void mainboard_smi_sleep(uint8_t slp_typ)
break;
}
switch (slp_typ) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
;
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) {

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@ -4,7 +4,6 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include "ec.h"
@ -33,24 +32,7 @@ void mainboard_smi_sleep(uint8_t slp_typ)
break;
}
switch (slp_typ) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
;
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(uint8_t apmc)

View File

@ -5,7 +5,6 @@
#include <cpu/x86/smm.h>
#include "ec.h"
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/smm.h>
#include <soc/pm.h>
@ -38,24 +37,7 @@ void mainboard_smi_sleep(uint8_t slp_typ)
break;
}
switch (slp_typ) {
case ACPI_S3:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
break;
case ACPI_S5:
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
break;
}
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
/* Clear pending events that may trigger immediate wake */
while (google_chromeec_get_event() != EC_HOST_EVENT_NONE)
;
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
/* Set LPC lines to low power in S3/S5. */
if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))