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nb/amd/mct_ddr3: Run fence training on each node after memory clock change 

The BKDG requires phy fences to be re-trained after a memory clock change.
Memory training on the ASUS KGPE-D16 and KCMA-D8 somehow "mostly" worked
 -- without actually following this requirement -- !

Fix the single typo that caused several weeks of delay in putting
servers with Kingston RAM (and others) into production...

Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Change-Id: I197e6728d2b0ac8c1535740599459d080b17af33
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14445
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2016-04-21 01:08:01 -05:00 committed by Martin Roth
parent 0b6ff78342
commit b474afdd21
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
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@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2015 - 2016 Raptor Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -2092,7 +2092,7 @@ void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat,
if (single_node_number >= 0) {
start_node = single_node_number;
end_node = single_node_number;
end_node = single_node_number + 1;
}
/* FIXME: skip for Ax */