mb/google/hatch: Correct PCIe ports setting for mushu

1. Enable PCIe port for dGPU
2. Change WLAN PCIe port from port 14 to port 7

BUG=b:147249494
TEST=Ensure dGPU and WLAN shows up with lspci.

Change-Id: Iea3292be7d8029c35847118228bbb773418632a1
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Amanda Huang 2020-02-04 11:36:43 +08:00 committed by Patrick Georgi
parent 3f5f74d134
commit b48148f4b3
1 changed files with 15 additions and 0 deletions

View File

@ -64,6 +64,21 @@ chip soc/intel/cannonlake
},
}"
# PCIe port 7 for M.2 E-key WLAN
register "PcieRpEnable[6]" = "1"
register "PcieRpLtrEnable[6]" = "1"
# RP 7 uses CLK SRC 3
register "PcieClkSrcUsage[3]" = "6"
register "PcieClkSrcClkReq[3]" = "3"
# Enable Root port 13 (x4) for dGPU
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
# RP 13 uses CLK SRC 5
register "PcieClkSrcUsage[5]" = "12"
# ClkReq-to-ClkSrc mapping for CLK SRC 5
register "PcieClkSrcClkReq[5]" = "5"
# GPIO for SD card detect
register "sdcard_cd_gpio" = "vSD3_CD_B"