soc/intel/alderlake: Update s0ix cstate table

Cstate C7 is not supported in ADL, replacing this unsupported state
with C6 in the s0ix cstate table.

BUG=None
TEST=Boot device to OS.
     Print supported CStates and latencies.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/acpi.c

@@ -107,7 +107,7 @@ static int cstate_set_non_s0ix[] = {
 
 static int cstate_set_s0ix[] = {
 	C_STATE_C1,
-	C_STATE_C7S_LONG_LAT,
+	C_STATE_C6_LONG_LAT,
 	C_STATE_C10
 };