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mainboard/google/poppy: Update DQS and DQ Byte mappings for poppy 

poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.

BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.

Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Rizwan Qureshi 2017-01-13 12:45:19 +05:30 committed by Duncan Laurie
parent 6f3a53b6f6
commit b4a159706e
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/poppy/romstage.c
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@ -25,14 +25,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
/* DQ byte map */
const u8 dq_map[2][12] = {
{ 0xF0, 0x0F, 0x00, 0xF0, 0x0F, 0xF0,
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
{ 0x33, 0xCC, 0x00, 0x33, 0xCC, 0x33,
{ 0xCC, 0x33, 0x00, 0x33, 0xCC, 0x33,
0xCC, 0x00, 0xFF, 0x00, 0xFF, 0x00 }
};
/* DQS CPU<>DRAM map */
const u8 dqs_map[2][8] = {
{ 0, 3, 1, 2, 4, 7, 6, 5 },
{ 2, 3, 1, 0, 4, 7, 6, 5 },
{ 5, 6, 0, 3, 4, 7, 2, 1 },
};
/* Rcomp resistor */