intel PCI ops: Remove explicit PCI MMCONF access

MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/broadwell/pcie.c

@@ -673,7 +673,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
 {
 	/* Set max snoop and non-snoop latency for Broadwell */
-	pci_mmio_write_config32(dev, off, 0x10031003);
+	pci_write_config32(dev, off, 0x10031003);
 }
 
 static struct pci_operations pcie_ops = {

src/soc/intel/skylake/pcie.c

@@ -75,7 +75,7 @@ static void pch_pcie_init(struct device *dev)
 static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off)
 {
 	/* Set max snoop and non-snoop latency for the SOC */
-	pci_mmio_write_config32(dev, off, 0x10031003);
+	pci_write_config32(dev, off, 0x10031003);
 }
 
 static struct pci_operations pcie_ops = {

src/southbridge/intel/bd82x6x/me.c

@@ -33,7 +33,7 @@
 #include <halt.h>
 
 #ifdef __SMM__
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>

src/southbridge/intel/bd82x6x/me_8.x.c

@@ -33,7 +33,7 @@
 #include <halt.h>
 
 #ifdef __SMM__
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>

src/southbridge/intel/bd82x6x/smihandler.c

@@ -28,7 +28,7 @@
 #include "nvs.h"
 
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/intel/model_206ax/model_206ax.h>

src/southbridge/intel/common/spi.c

@@ -35,7 +35,7 @@
 
 
 #ifdef __SMM__
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\

src/southbridge/intel/fsp_bd82x6x/azalia.c

@@ -245,28 +245,28 @@ static void azalia_init(struct device *dev)
 	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
 
 	if (RCBA32(0x2030) & (1 << 31)) {
-		reg32 = pci_mmio_read_config32(dev, 0x120);
+		reg32 = pci_read_config32(dev, 0x120);
 		reg32 &= 0xf8ffff01;
 		reg32 |= (1 << 24); // 25 for server
 		reg32 |= RCBA32(0x2030) & 0xfe;
-		pci_mmio_write_config32(dev, 0x120, reg32);
+		pci_write_config32(dev, 0x120, reg32);
 
-		reg16 = pci_mmio_read_config16(dev, 0x78);
+		reg16 = pci_read_config16(dev, 0x78);
 		reg16 &= ~(1 << 11);
-		pci_mmio_write_config16(dev, 0x78, reg16);
+		pci_write_config16(dev, 0x78, reg16);
 	} else
 		printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
 
-	reg32 = pci_mmio_read_config32(dev, 0x114);
+	reg32 = pci_read_config32(dev, 0x114);
 	reg32 &= ~0xfe;
-	pci_mmio_write_config32(dev, 0x114, reg32);
+	pci_write_config32(dev, 0x114, reg32);
 
 	// Set VCi enable bit
-	if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) |
+	if (pci_read_config32(dev, 0x120) & ((1 << 24) |
 						(1 << 25) | (1 << 26))) {
-		reg32 = pci_mmio_read_config32(dev, 0x120);
+		reg32 = pci_read_config32(dev, 0x120);
 		reg32 |= (1 << 31);
-		pci_mmio_write_config32(dev, 0x120, reg32);
+		pci_write_config32(dev, 0x120, reg32);
 	}
 
 	// Enable HDMI codec:

src/southbridge/intel/fsp_rangeley/spi.c

@@ -28,7 +28,7 @@
 static int ich_status_poll(u16 bitmask, int wait_til_set);
 
 #ifdef __SMM__
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #define pci_read_config_byte(dev, reg, targ)\
 	*(targ) = pci_read_config8(dev, reg)
 #define pci_read_config_word(dev, reg, targ)\

src/southbridge/intel/i82801gx/smihandler.c

@@ -212,7 +212,6 @@ static u32 reset_tco_status(void)
 	return reg32;
 }
 
-
 static void dump_tco_status(u32 tco_sts)
 {
 	printk(BIOS_DEBUG, "TCO_STS: ");
@@ -232,12 +231,6 @@ static void dump_tco_status(u32 tco_sts)
 	printk(BIOS_DEBUG, "\n");
 }
 
-/* We are using PCIe accesses for now
- *  1. the chipset can do it
- *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-#include <arch/pci_mmio_cfg.h>
-
 int southbridge_io_trap_handler(int smif)
 {
 	switch (smif) {

src/southbridge/intel/ibexpeak/me.c

@@ -32,7 +32,7 @@
 #include <elog.h>
 
 #ifdef __SMM__
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #else
 # include <device/device.h>
 # include <device/pci.h>

src/southbridge/intel/ibexpeak/smihandler.c

@@ -33,7 +33,7 @@
  */
 #include "northbridge/intel/nehalem/nehalem.h"
 #include <southbridge/intel/common/gpio.h>
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 
 /* While we read PMBASE dynamically in case it changed, let's
  * initialize it with a sane value