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nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings 

When programming the final dram attribute and dram boundary settings,
on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM
Refresh Control) register as documented in "Intel ® 4 Series Chipset
Family" documentation.

Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans 2017-12-25 20:17:41 +01:00 committed by Martin Roth
parent b5170c3e92
commit b4a78045d5
1 changed files with 8 additions and 0 deletions
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8
src/northbridge/intel/x4x/raminit_ddr23.c
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@ -1616,6 +1616,14 @@ static void set_dradrb(struct sysinfo *s)
MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0);
MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0);
if (s->spd_type == DDR3) {
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
/* ZQCAL enable */
MCHBAR32(0x269 + 0x400 * ch) =
MCHBAR32(0x269 + 0x400 * ch) | (1 << 26);
}
}
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) ||
ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
MCHBAR8(0x260) = MCHBAR8(0x260) | 1;