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soc/amd: Remove unsupported DPTC tablet mode settings 

The following boards are setting DTPC tablet mode values without
corresponding device tree values, meaning they are effectively setting
"random" values for tablet mode:
1. Cezanne
2. Mendocino

The device tree has tablet mode disabled, so the code should never be
exercised, but this CL removes it entirely to cleanup "dead" code.

BRANCH=none
BUG=b:217911928
TEST=Build nipperkin
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Tim Van Patten 2022-08-29 12:11:27 -06:00 committed by Felix Held
parent c8a86954f3
commit b4b85ebf60
4 changed files with 4 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/soc/amd/cezanne/chip.h
View File

@ -86,14 +86,7 @@ struct soc_amd_cezanne_config {
uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset;
/* Enable dptc tablet mode */
bool dptc_tablet_mode_enable;
/* STAPM Configuration for tablet mode */
uint32_t fast_ppt_limit_tablet_mode_mW;
uint32_t slow_ppt_limit_tablet_mode_mW;
uint32_t sustained_power_limit_tablet_mode_mW;
uint32_t thermctl_limit_tablet_mode_degreeC;
bool dptc_enable;
/* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */

11
src/soc/amd/cezanne/root_complex.c
View File

@ -186,7 +186,7 @@ static void acipgen_dptci(void)
{
const struct soc_amd_cezanne_config *config = config_of_soc();
if (!config->dptc_tablet_mode_enable)
if (!config->dptc_enable)
return;
/* DPTC is enabled. Always fill out the default DPTC values. */
@ -195,15 +195,6 @@ static void acipgen_dptci(void)
config->fast_ppt_limit_mW,
config->slow_ppt_limit_mW);
acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
/* Tablet Mode */
struct dptc_input tablet_mode_input = DPTC_INPUTS(
config->thermctl_limit_tablet_mode_degreeC,
config->sustained_power_limit_tablet_mode_mW,
config->fast_ppt_limit_tablet_mode_mW,
config->slow_ppt_limit_tablet_mode_mW);
acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_mode_input,
sizeof(tablet_mode_input));
}
static void root_complex_fill_ssdt(const struct device *device)

9
src/soc/amd/mendocino/chip.h
View File

@ -82,14 +82,7 @@ struct soc_amd_mendocino_config {
uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset;
/* Enable dptc tablet mode */
bool dptc_tablet_mode_enable;
/* STAPM Configuration for tablet mode */
uint32_t fast_ppt_limit_tablet_mode_mW;
uint32_t slow_ppt_limit_tablet_mode_mW;
uint32_t sustained_power_limit_tablet_mode_mW;
uint32_t thermctl_limit_tablet_mode_degreeC;
bool dptc_enable;
/* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */

11
src/soc/amd/mendocino/root_complex.c
View File

@ -188,7 +188,7 @@ static void acipgen_dptci(void)
{
const struct soc_amd_mendocino_config *config = config_of_soc();
if (!config->dptc_tablet_mode_enable)
if (!config->dptc_enable)
return;
/* DPTC is enabled. Always fill out the default DPTC values. */
@ -197,15 +197,6 @@ static void acipgen_dptci(void)
config->fast_ppt_limit_mW,
config->slow_ppt_limit_mW);
acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input));
/* Tablet Mode */
struct dptc_input tablet_mode_input = DPTC_INPUTS(
config->thermctl_limit_tablet_mode_degreeC,
config->sustained_power_limit_tablet_mode_mW,
config->fast_ppt_limit_tablet_mode_mW,
config->slow_ppt_limit_tablet_mode_mW);
acpigen_write_alib_dptc_tablet((uint8_t *)&tablet_mode_input,
sizeof(tablet_mode_input));
}
static void root_complex_fill_ssdt(const struct device *device)