diff --git a/src/soc/mediatek/common/gpio_op.c b/src/soc/mediatek/common/gpio_op.c new file mode 100644 index 0000000000..a45e54390c --- /dev/null +++ b/src/soc/mediatek/common/gpio_op.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 + (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits32(reg1, BIT(bit)); + else + clrbits32(reg1, BIT(bit)); + } + + if (enable == GPIO_PULL_ENABLE) { + setbits32(reg2, BIT(bit)); + } else { + clrbits32(reg2, BIT(bit)); + clrbits32(reg2 + 0x010, BIT(bit)); + } +} + +static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg1; + void *reg2; + int bit = gpio.bit; + + reg1 = gpio_find_reg_addr(gpio) + gpio.offset; + reg2 = reg1 - (gpio.base & 0xf0); + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) { + clrbits32(reg1, BIT(bit)); + setbits32(reg2, BIT(bit)); + } else { + clrbits32(reg2, BIT(bit)); + setbits32(reg1, BIT(bit)); + } + } else { + clrbits32(reg1, BIT(bit)); + clrbits32(reg2, BIT(bit)); + } +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_spec_pull_pupd(gpio, enable, select); + else + gpio_set_pull_pu_pd(gpio, enable, select); +} diff --git a/src/soc/mediatek/common/include/soc/gpio_common.h b/src/soc/mediatek/common/include/soc/gpio_common.h index 097c2b9525..f0cbb04366 100644 --- a/src/soc/mediatek/common/include/soc/gpio_common.h +++ b/src/soc/mediatek/common/include/soc/gpio_common.h @@ -42,6 +42,7 @@ struct gpio_drv_info { void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); void gpio_set_mode(gpio_t gpio, int mode); +void *gpio_find_reg_addr(gpio_t gpio); /* Normal driving function */ int gpio_set_driving(gpio_t gpio, uint8_t drv); diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index fa353ae2dc..8b0e52a8e9 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -2,7 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y) # for bootblock, verstage, romstage, ramstage all-y += ../common/flash_controller.c -all-y += ../common/gpio.c gpio.c +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-y += ../common/i2c.c i2c.c all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c all-y += ../common/timer.c ../common/timer_prepare.c diff --git a/src/soc/mediatek/mt8186/gpio.c b/src/soc/mediatek/mt8186/gpio.c index c96f1ea2ac..59143461a7 100644 --- a/src/soc/mediatek/mt8186/gpio.c +++ b/src/soc/mediatek/mt8186/gpio.c @@ -223,7 +223,7 @@ static const struct gpio_drv_info gpio_driving_adv_info[GPIO_NUM] = { [146] = { 0x20, 15, 3, }, }; -static void *gpio_find_reg_addr(gpio_t gpio) +void *gpio_find_reg_addr(gpio_t gpio) { void *reg_addr; switch (gpio.base & 0x0f) { @@ -253,64 +253,6 @@ static void *gpio_find_reg_addr(gpio_t gpio) return reg_addr; } -static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - void *reg1; - void *reg2; - int bit = gpio.bit; - - reg1 = gpio_find_reg_addr(gpio) + gpio.offset; - reg2 = reg1 + (gpio.base & 0xf0); - - if (enable == GPIO_PULL_ENABLE) { - if (select == GPIO_PULL_DOWN) - setbits32(reg1, BIT(bit)); - else - clrbits32(reg1, BIT(bit)); - } - - if (enable == GPIO_PULL_ENABLE) { - setbits32(reg2, 1 << bit); - } else { - clrbits32(reg2, 1 << bit); - clrbits32(reg2 + 0x010, BIT(bit)); - } -} - -static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - void *reg1; - void *reg2; - int bit = gpio.bit; - - reg1 = gpio_find_reg_addr(gpio) + gpio.offset; - reg2 = reg1 - (gpio.base & 0xf0); - - if (enable == GPIO_PULL_ENABLE) { - if (select == GPIO_PULL_DOWN) { - clrbits32(reg1, BIT(bit)); - setbits32(reg2, BIT(bit)); - } else { - clrbits32(reg2, BIT(bit)); - setbits32(reg1, BIT(bit)); - } - } else { - clrbits32(reg1, BIT(bit)); - clrbits32(reg2, BIT(bit)); - } -} - -void gpio_set_pull(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - if (gpio.flag) - gpio_set_spec_pull_pupd(gpio, enable, select); - else - gpio_set_pull_pu_pd(gpio, enable, select); -} - static inline bool is_valid_drv(uint8_t drv) { return drv <= GPIO_DRV_16_MA; diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index fd983d5b0e..3e3f59ae15 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -2,7 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) # for bootblock, verstage, romstage, ramstage all-y += ../common/flash_controller.c -all-y += ../common/gpio.c gpio.c +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-y += ../common/i2c.c i2c.c all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c all-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/gpio.c b/src/soc/mediatek/mt8192/gpio.c index dcc133299c..b10ff58731 100644 --- a/src/soc/mediatek/mt8192/gpio.c +++ b/src/soc/mediatek/mt8192/gpio.c @@ -4,7 +4,7 @@ #include #include -static void *gpio_find_reg_addr(gpio_t gpio) +void *gpio_find_reg_addr(gpio_t gpio) { void *reg_addr; switch (gpio.base & 0x0f) { @@ -42,61 +42,3 @@ static void *gpio_find_reg_addr(gpio_t gpio) return reg_addr; } - -static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - void *reg1; - void *reg2; - int bit = gpio.bit; - - reg1 = gpio_find_reg_addr(gpio) + gpio.offset; - reg2 = reg1 + (gpio.base & 0xf0); - - if (enable == GPIO_PULL_ENABLE) { - if (select == GPIO_PULL_DOWN) - setbits32(reg1, 1 << bit); - else - clrbits32(reg1, 1 << bit); - } - - if (enable == GPIO_PULL_ENABLE) - setbits32(reg2, 1 << bit); - else { - clrbits32(reg2, 1 << bit); - clrbits32(reg2 + 0x010, 1 << bit); - } -} - -static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - void *reg1; - void *reg2; - int bit = gpio.bit; - - reg1 = gpio_find_reg_addr(gpio) + gpio.offset; - reg2 = reg1 - (gpio.base & 0xf0); - - if (enable == GPIO_PULL_ENABLE) { - if (select == GPIO_PULL_DOWN) { - clrbits32(reg1, 1 << bit); - setbits32(reg2, 1 << bit); - } else { - clrbits32(reg2, 1 << bit); - setbits32(reg1, 1 << bit); - } - } else { - clrbits32(reg1, 1 << bit); - clrbits32(reg2, 1 << bit); - } -} - -void gpio_set_pull(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - if (gpio.flag) - gpio_set_spec_pull_pupd(gpio, enable, select); - else - gpio_set_pull_pu_pd(gpio, enable, select); -} diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index b0d259e3a1..b8c36d1625 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -2,7 +2,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) # for bootblock, verstage, romstage, ramstage all-y += ../common/flash_controller.c -all-y += ../common/gpio.c gpio.c +all-y += ../common/gpio.c ../common/gpio_op.c gpio.c all-y += ../common/i2c.c i2c.c all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c all-y += ../common/timer.c ../common/timer_prepare.c diff --git a/src/soc/mediatek/mt8195/gpio.c b/src/soc/mediatek/mt8195/gpio.c index 9c741f824a..f344c09dc2 100644 --- a/src/soc/mediatek/mt8195/gpio.c +++ b/src/soc/mediatek/mt8195/gpio.c @@ -3,7 +3,7 @@ #include #include -static void *gpio_find_reg_addr(gpio_t gpio) +void *gpio_find_reg_addr(gpio_t gpio) { void *reg_addr; switch (gpio.base & 0x0f) { @@ -32,61 +32,3 @@ static void *gpio_find_reg_addr(gpio_t gpio) return reg_addr; } - -static void gpio_set_spec_pull_pupd(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - void *reg1; - void *reg2; - int bit = gpio.bit; - - reg1 = gpio_find_reg_addr(gpio) + gpio.offset; - reg2 = reg1 + (gpio.base & 0xf0); - - if (enable == GPIO_PULL_ENABLE) { - if (select == GPIO_PULL_DOWN) - setbits32(reg1, 1 << bit); - else - clrbits32(reg1, 1 << bit); - } - - if (enable == GPIO_PULL_ENABLE) { - setbits32(reg2, 1 << bit); - } else { - clrbits32(reg2, 1 << bit); - clrbits32(reg2 + 0x010, 1 << bit); - } -} - -static void gpio_set_pull_pu_pd(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - void *reg1; - void *reg2; - int bit = gpio.bit; - - reg1 = gpio_find_reg_addr(gpio) + gpio.offset; - reg2 = reg1 - (gpio.base & 0xf0); - - if (enable == GPIO_PULL_ENABLE) { - if (select == GPIO_PULL_DOWN) { - clrbits32(reg1, 1 << bit); - setbits32(reg2, 1 << bit); - } else { - clrbits32(reg2, 1 << bit); - setbits32(reg1, 1 << bit); - } - } else { - clrbits32(reg1, 1 << bit); - clrbits32(reg2, 1 << bit); - } -} - -void gpio_set_pull(gpio_t gpio, enum pull_enable enable, - enum pull_select select) -{ - if (gpio.flag) - gpio_set_spec_pull_pupd(gpio, enable, select); - else - gpio_set_pull_pu_pd(gpio, enable, select); -}