GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/rex: Add fingerprint SPI 

Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce631 ("Invoke power cycle of
FPMCU on startup")

TEST=Tested on Rex - setup and logged in using fingerprint

Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eran Mitrani 2022-08-23 14:42:24 -07:00 committed by Subrata Banik
parent 425413c35f
commit b4d71e1ab2
3 changed files with 21 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/rex/Kconfig
View File

@ -8,6 +8,7 @@ config BOARD_GOOGLE_REX_COMMON
select DRIVERS_SOUNDWIRE_ALC5682
select DRIVERS_WIFI_GENERIC
select DRIVERS_INTEL_MIPI_CAMERA
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI

6
src/mainboard/google/rex/variants/rex0/gpio.c
View File

@ -432,8 +432,12 @@ static const struct pad_config default_early_gpio_table[] = {
};
static const struct pad_config romstage_gpio_table_id0[] = {
/* A20 : [] ==> SSD_PERST_L */
/* GPP_B11 : [] ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_B11, 0, DEEP),
/* A20 : [] ==> SSD_PERST_L */
PAD_CFG_GPO(GPP_A20, 0, DEEP),
/* GPP_C23 : [] ==> FP_RST_ODL */
PAD_CFG_GPO(GPP_C23, 0, DEEP),
/* GPP_E07 : [] ==> WWAN_FCPO_L */
PAD_CFG_GPO(GPP_E07, 1, DEEP),
};

16
src/mainboard/google/rex/variants/rex0/overridetree.cb
View File

@ -471,7 +471,21 @@ chip soc/intel/meteorlake
device generic 0 on end
end
end #PCIE6 WWAN card
device ref gspi1 on end
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)"
register "wake" = "GPE0_DW1_10"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
register "enable_delay_ms" = "3"
device spi 0 on end
end # FPMCU
end
device ref soc_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]