mb/google/rex: Add fingerprint SPI
Add Fingerprint SPI, and power-off FPMCU during romstage.
For reference see CL:66915 for a similar change to Brya's power sequence
SHA: 2b523ce631
("Invoke power cycle of
FPMCU on startup")
TEST=Tested on Rex - setup and logged in using fingerprint
Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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@ -8,6 +8,7 @@ config BOARD_GOOGLE_REX_COMMON
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select DRIVERS_SOUNDWIRE_ALC5682
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select DRIVERS_SOUNDWIRE_ALC5682
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select DRIVERS_WIFI_GENERIC
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select DRIVERS_WIFI_GENERIC
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_INTEL_MIPI_CAMERA
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select DRIVERS_SPI_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ESPI
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select EC_GOOGLE_CHROMEEC_ESPI
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@ -432,8 +432,12 @@ static const struct pad_config default_early_gpio_table[] = {
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};
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};
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static const struct pad_config romstage_gpio_table_id0[] = {
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static const struct pad_config romstage_gpio_table_id0[] = {
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/* GPP_B11 : [] ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_B11, 0, DEEP),
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/* A20 : [] ==> SSD_PERST_L */
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/* A20 : [] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_A20, 0, DEEP),
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PAD_CFG_GPO(GPP_A20, 0, DEEP),
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/* GPP_C23 : [] ==> FP_RST_ODL */
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PAD_CFG_GPO(GPP_C23, 0, DEEP),
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/* GPP_E07 : [] ==> WWAN_FCPO_L */
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/* GPP_E07 : [] ==> WWAN_FCPO_L */
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PAD_CFG_GPO(GPP_E07, 1, DEEP),
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PAD_CFG_GPO(GPP_E07, 1, DEEP),
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};
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};
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@ -471,7 +471,21 @@ chip soc/intel/meteorlake
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device generic 0 on end
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device generic 0 on end
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end
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end
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end #PCIE6 WWAN card
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end #PCIE6 WWAN card
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device ref gspi1 on end
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device ref gspi1 on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)"
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register "wake" = "GPE0_DW1_10"
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register "has_power_resource" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)"
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register "enable_delay_ms" = "3"
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device spi 0 on end
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end # FPMCU
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end
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device ref soc_espi on
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device ref soc_espi on
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chip ec/google/chromeec
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn0 as mux_conn[0]
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