mb/google/hatch: Default GSPI1 (FPR) to off in baseboard

Default GSPI1 (fingerprint reader) to off in baseboard, since all
variants which use one already enable it in their override tree.
This allows variants which do not use it to drop it from their
override trees.

Change-Id: I07979e35b67635ceadd3906e37de177dd081d35a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78547
Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2023-10-22 13:24:52 -05:00 committed by Matt DeVillier
parent 1a59390f2d
commit b4eff88cbb
5 changed files with 1 additions and 6 deletions

View File

@ -234,7 +234,6 @@ chip soc/intel/cannonlake
end
end #I2C #4
device pci 1a.0 on end # eMMC
device pci 1e.3 off end # GSPI #1
device pci 1f.3 on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""

View File

@ -337,7 +337,7 @@ chip soc/intel/cannonlake
device spi 0 on end
end
end # GSPI #0
device pci 1e.3 on end # GSPI #1
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on
chip ec/google/chromeec
device pnp 0c09.0 on end

View File

@ -203,7 +203,6 @@ chip soc/intel/cannonlake
end
end #I2C #4
device pci 1a.0 on end # eMMC
device pci 1e.3 off end # GSPI #1 unused
device pci 1f.3 on
chip drivers/generic/max98357a
register "hid" = ""MX98357A""

View File

@ -262,7 +262,6 @@ chip soc/intel/cannonlake
# No PCIe WiFi
device pci 1d.5 off end
device pci 1a.0 on end #eMMC
device pci 1e.3 off end # GSPI #1
device pci 1f.3 on
chip drivers/sof
register "spkr_tplg" = "max98390"

View File

@ -183,8 +183,6 @@ chip soc/intel/cannonlake
device i2c 39 on end
end
end #I2C #4
# GSPI #1 unused
device pci 1e.3 off end
device pci 1f.3 on
chip drivers/generic/max98357a