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intel cache-as-ram: Fix comment about MTRRs 

Change-Id: I5b9e10fe119c1a046494235e85f730bedfe8578d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-21 06:59:30 +03:00
parent e00b2de71c
commit b4f827d45a
3 changed files with 6 additions and 6 deletions
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4
src/cpu/intel/car/cache_as_ram.inc
View File

@ -321,8 +321,8 @@ lout:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
/* We don't need CAR from now on. */

4
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@ -342,8 +342,8 @@ no_msr_11e:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
post_code(0x30)

4
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -135,8 +135,8 @@ clear_mtrrs:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
post_code(0x2f)