rk3288: Pass SPI bus speed in as parameter to init function
This re-factors rockchip_spi to remove speed_hz which will instead be passed in via rockchip_spi_init(), thus making it easier to support other boards which may have different slave devices attached. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10 Original-Reviewed-on: https://chromium-review.googlesource.com/220411 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c Reviewed-on: http://review.coreboot.org/9245 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
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@ -32,11 +32,11 @@ void bootblock_mainboard_init(void)
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/* spi2 for firmware ROM */
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/* spi2 for firmware ROM */
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writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
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writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
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writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
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writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
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rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
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rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000);
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/* spi0 for chrome ec */
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/* spi0 for chrome ec */
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writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
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writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000);
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setup_chromeos_gpios();
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setup_chromeos_gpios();
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}
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}
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@ -33,7 +33,6 @@
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struct rockchip_spi_slave {
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struct rockchip_spi_slave {
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struct spi_slave slave;
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struct spi_slave slave;
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struct rockchip_spi *regs;
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struct rockchip_spi *regs;
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unsigned int speed_hz;
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unsigned int fifo_size;
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unsigned int fifo_size;
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};
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};
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@ -47,13 +46,11 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = {
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.rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
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.rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
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},
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},
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.regs = (void *)SPI0_BASE,
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.regs = (void *)SPI0_BASE,
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.speed_hz = 9000000,
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.fifo_size = 32,
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.fifo_size = 32,
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},
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},
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{
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{
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.slave = {.bus = 1, .rw = SPI_READ_FLAG,},
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.slave = {.bus = 1, .rw = SPI_READ_FLAG,},
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.regs = (void *)SPI1_BASE,
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.regs = (void *)SPI1_BASE,
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.speed_hz = 11000000,
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.fifo_size = 32,
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.fifo_size = 32,
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},
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},
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{
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{
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@ -62,7 +59,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = {
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.rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
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.rw = SPI_READ_FLAG | SPI_WRITE_FLAG,
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},
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},
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.regs = (void *)SPI2_BASE,
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.regs = (void *)SPI2_BASE,
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.speed_hz = 11000000,
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.fifo_size = 32,
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.fifo_size = 32,
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},
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},
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@ -110,7 +106,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
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writel(clk_div, ®s->baudr);
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writel(clk_div, ®s->baudr);
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}
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}
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void rockchip_spi_init(unsigned int bus)
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void rockchip_spi_init(unsigned int bus, unsigned int speed_hz)
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{
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{
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struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus];
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struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus];
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struct rockchip_spi *regs = espi->regs;
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struct rockchip_spi *regs = espi->regs;
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@ -118,7 +114,7 @@ void rockchip_spi_init(unsigned int bus)
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rkclk_configure_spi(bus, SPI_SRCCLK_HZ);
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rkclk_configure_spi(bus, SPI_SRCCLK_HZ);
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rockchip_spi_enable_chip(regs, 0);
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rockchip_spi_enable_chip(regs, 0);
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rockchip_spi_set_clk(regs, espi->speed_hz);
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rockchip_spi_set_clk(regs, speed_hz);
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/* Operation Mode */
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/* Operation Mode */
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ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET);
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ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET);
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@ -199,6 +199,6 @@ check_member(rockchip_spi, rxdr, 0x800);
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int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media,
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int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media,
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void *buffer_address,
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void *buffer_address,
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size_t buffer_size);
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size_t buffer_size);
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void rockchip_spi_init(unsigned int bus);
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void rockchip_spi_init(unsigned int bus, unsigned int speed_hz);
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#endif
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#endif
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