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baytrail: Fix _CRS to build with new IASL 

The new IASL is complaining about the PCI memory region not
having consistent base/end/length values because they are
placeholder that are fixed up in the method before returning.

Put in some more valid placeholder values to make it happy.

BUG=chromium:311294
BRANCH=none
TEST=build and boot with IASL 20130117 on rambi

Change-Id: I0e21adcce43deb14d3c2c45787ff8c9efc357c2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178864
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4988
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie 2013-12-04 18:34:11 -08:00 committed by Kyösti Mälkki
parent ac9a905cf1
commit b50566ef63
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/baytrail/acpi/southcluster.asl
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@ -160,8 +160,8 @@ Method (_CRS, 0, Serialized)
// PCI Memory Region (Top of memory-0xfeafffff) // PCI Memory Region (Top of memory-0xfeafffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite, Cacheable, ReadWrite,
0x00000000, 0x00000000, 0xfeafffff, 0x00000000, 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000,
0xfeb00000,,, PMEM) 0x00100000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff) // TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,