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nb/intel/sandybridge: Add x86_64 support

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Fix compilation on x86_64 by using compatible types.
The MRC blob isn't supported yet as there's no x86_32 wrapper.

Tested on HP8200:
* Still boots on x86_32.
* Boots to payload in x86_64

Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2020-08-20 16:50:01 +02:00 committed by Patrick Georgi
parent ed8d777cec
commit b50b6a5fa7
5 changed files with 40 additions and 25 deletions
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8
src/cpu/intel/model_206ax/Kconfig
View file

@ -3,9 +3,15 @@ config CPU_INTEL_MODEL_206AX
if CPU_INTEL_MODEL_206AX
config ARCH_EXP_X86_64
bool "Experimental 64bit support"
depends on USE_NATIVE_RAMINIT
default n
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_ALL_STAGES_X86_32
select ARCH_ALL_STAGES_X86_32 if !ARCH_EXP_X86_64
select ARCH_ALL_STAGES_X86_64 if ARCH_EXP_X86_64
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select MMX
select SSE2

29
src/northbridge/intel/sandybridge/raminit_common.c
View file

@ -1509,9 +1509,12 @@ static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b)
{
unsigned int j;
unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
uintptr_t addr;
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + 4 * j;
write32((void *)addr, j & 2 ? b : a);
}
sfence();
@ -1531,13 +1534,16 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel)
unsigned int j;
unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 64;
unsigned int channel_step = 64 * num_of_channels(ctrl);
uintptr_t addr;
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
for (j = 0; j < 16; j++)
write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0);
for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + j * 4;
write32((void *)addr, 0xffffffff);
}
for (j = 0; j < 16; j++) {
addr = 0x04000000 + channel_offset + channel_step + j * 4;
write32((void *)addr, 0);
}
sfence();
program_wdb_pattern_length(channel, 16);
@ -1929,6 +1935,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
unsigned int i, j;
unsigned int offset = get_precedening_channels(ctrl, channel) * 64;
unsigned int step = 64 * num_of_channels(ctrl);
uintptr_t addr;
if (patno) {
u8 base8 = 0x80 >> ((patno - 1) % 8);
@ -1940,14 +1947,16 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno)
if (invert[patno - 1][i] & (1 << (j / 2)))
val = ~val;
write32((void *)((1 << 26) + offset + i * step + j * 4), val);
addr = (1 << 26) + offset + i * step + j * 4;
write32((void *)addr, val);
}
}
} else {
for (i = 0; i < ARRAY_SIZE(pattern); i++) {
for (j = 0; j < 16; j++) {
const u32 val = pattern[i][j];
write32((void *)((1 << 26) + offset + i * step + j * 4), val);
addr = (1 << 26) + offset + i * step + j * 4;
write32((void *)addr, val);
}
}
sfence();

2
src/southbridge/intel/bd82x6x/azalia.c
View file

@ -165,7 +165,7 @@ static void azalia_init(struct device *dev)
// NOTE this will break as soon as the Azalia get's a bar above 4G.
// Is there anything we can do about it?
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
if (RCBA32(CIR31) & (1 << 31)) {
reg32 = pci_read_config32(dev, 0x120);

24
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -258,18 +258,18 @@ static void cpt_pm_init(struct device *dev)
{
printk(BIOS_DEBUG, "CougarPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
RCBA32_AND_OR(CIR30, ~0UL, (1 << 6)|(1 << 0));
RCBA32_AND_OR(CIR5, ~0UL, (1 << 0));
RCBA16_AND_OR(CIR3, ~0UL, (1 << 13)|(1 << 14));
RCBA16_AND_OR(CIR2, ~0UL, (1 << 14));
RCBA32_AND_OR(CIR30, ~0U, (1 << 6)|(1 << 0));
RCBA32_AND_OR(CIR5, ~0U, (1 << 0));
RCBA16_AND_OR(CIR3, ~0U, (1 << 13)|(1 << 14));
RCBA16_AND_OR(CIR2, ~0U, (1 << 14));
RCBA32(DMC) = 0xc0388400;
RCBA32_AND_OR(CIR6, ~0UL, (1 << 5)|(1 << 18));
RCBA32_AND_OR(CIR9, ~0UL, (1 << 15)|(1 << 1));
RCBA32_AND_OR(CIR6, ~0U, (1 << 5)|(1 << 18));
RCBA32_AND_OR(CIR9, ~0U, (1 << 15)|(1 << 1));
RCBA32_AND_OR(CIR7, ~0x1f, 0xf);
RCBA32(PM_CFG) = 0x050f0000;
RCBA32(CIR8) = 0x04000000;
RCBA32_AND_OR(CIR10, ~0UL, 0xfffff);
RCBA32_AND_OR(CIR11, ~0UL, (1 << 1));
RCBA32_AND_OR(CIR10, ~0U, 0xfffff);
RCBA32_AND_OR(CIR11, ~0U, (1 << 1));
RCBA32(CIR12) = 0x0001c000;
RCBA32(CIR14) = 0x00061100;
RCBA32(CIR15) = 0x7f8fdfff;
@ -371,10 +371,10 @@ static void enable_clock_gating(struct device *dev)
reg16 |= (1 << 11);
pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
pch_iobp_update(0xEB007F07, ~0U, (1 << 31));
pch_iobp_update(0xEB004000, ~0U, (1 << 7));
pch_iobp_update(0xEC007F07, ~0U, (1 << 31));
pch_iobp_update(0xEC004000, ~0U, (1 << 7));
reg32 = RCBA32(CG);
reg32 |= (1 << 31);

2
src/southbridge/intel/bd82x6x/sata.c
View file

@ -126,7 +126,7 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */
abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
abar = (u8 *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);