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Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown" 

This reverts commit 7ef5376123.

Reason for revert: It was merged before its dependencies so now master is broken.

Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2022-09-20 18:07:56 +00:00 committed by Martin L Roth
parent 19491c526d
commit b525ea726b
1 changed files with 5 additions and 8 deletions
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13
src/soc/intel/apollolake/chip.c
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@ -16,7 +16,6 @@
#include <intelblocks/p2sb.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
@ -698,13 +697,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
/* coreboot handles the lockdown */
silconfig->LockDownGlobalSmi = 0;
silconfig->BiosLock = 0;
silconfig->BiosInterface = 0;
silconfig->WriteProtectionEnable[0] = 0;
silconfig->SpiEiss = 0;
silconfig->RtcLock = 0;
/* Disable setting of EISS bit in FSP. */
silconfig->SpiEiss = 0;
/* Disable FSP from locking access to the RTC NVRAM */
silconfig->RtcLock = 0;
/* Enable Audio clk gate and power gate */
silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;