soc/intel/baytrail: Rename "pmc.h" to "pm.h"

This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

src/mainboard/google/rambi/irqroute.h

@@ -2,7 +2,7 @@
 
 #include <soc/irq.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 
 #define PCI_DEV_PIRQ_ROUTES \
 	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \

src/mainboard/google/rambi/mainboard_smi.c

@@ -11,7 +11,7 @@
 #include "ec.h"
 
 #include <soc/nvs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 
 /* The wake gpio is SUS_GPIO[0]. */
 #define WAKE_GPIO_EN SUS_GPIO_EN0

src/soc/intel/baytrail/acpi.c

@@ -18,7 +18,7 @@
 #include <soc/irq.h>
 #include <soc/msr.h>
 #include <soc/pattrs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 
 #include <ec/google/chromeec/ec.h>
 #include <vendorcode/google/chromeos/gnvs.h>

src/soc/intel/baytrail/bootblock/bootblock.c

@@ -7,7 +7,7 @@
 #include <soc/gpio.h>
 #include <soc/lpc.h>
 #include <soc/spi.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 
 static void setup_mmconfig(void)
 {

src/soc/intel/baytrail/ehci.c

@@ -10,7 +10,7 @@
 #include <soc/iomap.h>
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/ehci.h>
 

src/soc/intel/baytrail/elog.c

@@ -8,7 +8,7 @@
 #include <device/pci.h>
 #include <elog.h>
 #include <soc/iomap.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 
 static void log_power_and_resets(const struct chipset_power_state *ps)
 {

src/soc/intel/baytrail/gpio.c

@@ -5,7 +5,7 @@
 #include <device/pci.h>
 #include <console/console.h>
 #include <soc/gpio.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/smm.h>
 
 /* GPIO-to-Pad LUTs */

src/soc/intel/baytrail/include/soc/pm.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef _BAYTRAIL_PMC_H_
-#define _BAYTRAIL_PMC_H_
+#ifndef _BAYTRAIL_PM_H_
+#define _BAYTRAIL_PM_H_
 
 #include <acpi/acpi.h>
 
@@ -275,4 +275,4 @@ int rtc_failure(void);
 
 #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
 
-#endif /* _BAYTRAIL_PMC_H_ */
+#endif /* _BAYTRAIL_PM_H_ */

src/soc/intel/baytrail/lpe.c

@@ -15,7 +15,7 @@
 #include <soc/nvs.h>
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include "chip.h"
 

src/soc/intel/baytrail/pmutil.c

@@ -14,7 +14,7 @@
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <security/vboot/vbnv.h>
 
 #if defined(__SIMPLE_DEVICE__)

src/soc/intel/baytrail/ramstage.c

@@ -18,7 +18,7 @@
 #include <soc/nvs.h>
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/iosf.h>
 

src/soc/intel/baytrail/romstage/pmc.c

@@ -9,7 +9,7 @@
 #include <soc/iosf.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/romstage.h>
 #include "../chip.h"
 

src/soc/intel/baytrail/romstage/romstage.c

@@ -17,7 +17,7 @@
 #include <soc/iomap.h>
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/romstage.h>
 
 static struct chipset_power_state power_state;

src/soc/intel/baytrail/smihandler.c

@@ -15,7 +15,7 @@
 
 #include <soc/iosf.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/nvs.h>
 
 static int smm_initialized;

src/soc/intel/baytrail/smm.c

@@ -8,7 +8,7 @@
 #include <cpu/x86/smm.h>
 #include <cpu/intel/smm_reloc.h>
 #include <soc/iomap.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/smm.h>
 
 /* Save settings which will be committed in SMI functions. */

src/soc/intel/baytrail/southcluster.c

@@ -22,7 +22,7 @@
 #include <soc/lpc.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/spi.h>
 #include "chip.h"

src/soc/intel/baytrail/xhci.c

@@ -14,7 +14,7 @@
 #include <soc/lpc.h>
 #include <soc/pattrs.h>
 #include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/xhci.h>