diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
index b4b746542e..5780f4c799 100644
--- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl
+++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl
@@ -276,6 +276,11 @@ Device (PDRC)
 			/* FLASH range */
 			Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
 
+#if CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW)
+			/* Extended BIOS window */
+			Memory32Fixed (ReadOnly, CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE)
+#endif
+
 			/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */
 			Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
 
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 4c5731f9ca..6b039e1c01 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -287,6 +287,11 @@ static void systemagent_read_resources(struct device *dev)
 	if (CONFIG(SA_ENABLE_IMR))
 		/* Add the isolated memory ranges (IMRs). */
 		sa_add_imr_resources(dev, &index);
+
+	/* Reserve the window used for extended BIOS decoding. */
+	if (CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
+		mmio_resource(dev, index++, CONFIG_EXT_BIOS_WIN_BASE / KiB,
+			      CONFIG_EXT_BIOS_WIN_SIZE / KiB);
 }
 
 void enable_power_aware_intr(void)