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soc/intel/skylake: Rename PcieRpAspm devicetree config 

This configuration option shares a name with the FSP UPD, but
is enumerated differently. Change its name to minimise confusion
about the options.

Change-Id: Id74f043ecd549bde4501320bff1dc080bde64057
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Benjamin Doron 2020-10-12 04:19:42 +00:00 committed by Nico Huber
parent 3f1de9add9
commit b53858bace
3 changed files with 6 additions and 6 deletions
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6
src/mainboard/facebook/monolith/devicetree.cb
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@ -151,7 +151,7 @@ chip soc/intel/skylake
# Enable Advanced Error Reporting # Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[2]" = "1" register "PcieRpAdvancedErrorReporting[2]" = "1"
# Disable Aspm # Disable Aspm
register "PcieRpAspm[2]" = "AspmDisabled" register "pcie_rp_aspm[2]" = "AspmDisabled"
# PCIE Port 4 disabled # PCIE Port 4 disabled
# PCIE Port 5 x1 -> MODULE i219 # PCIE Port 5 x1 -> MODULE i219
@ -166,7 +166,7 @@ chip soc/intel/skylake
# Enable Advanced Error Reporting # Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[5]" = "1" register "PcieRpAdvancedErrorReporting[5]" = "1"
# Disable Aspm # Disable Aspm
register "PcieRpAspm[5]" = "AspmDisabled" register "pcie_rp_aspm[5]" = "AspmDisabled"
# PCIE Port 7 Disabled # PCIE Port 7 Disabled
# PCIE Port 8 Disabled # PCIE Port 8 Disabled
@ -184,7 +184,7 @@ chip soc/intel/skylake
# Enable Advanced Error Reporting # Enable Advanced Error Reporting
register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpAdvancedErrorReporting[8]" = "1"
# Disable Aspm # Disable Aspm
register "PcieRpAspm[8]" = "AspmDisabled" register "pcie_rp_aspm[8]" = "AspmDisabled"
# USB 2.0 Enable all ports # USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2

4
src/soc/intel/skylake/chip.c
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@ -210,8 +210,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->PcieRpHotPlug)); sizeof(params->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
if (config->PcieRpAspm[i]) if (config->pcie_rp_aspm[i])
params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1;
if (config->pcie_rp_l1substates[i]) if (config->pcie_rp_l1substates[i])
params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
} }

2
src/soc/intel/skylake/chip.h
View File

@ -262,7 +262,7 @@ struct soc_intel_skylake_config {
AspmL1, AspmL1,
AspmL0sL1, AspmL0sL1,
AspmAutoConfig, AspmAutoConfig,
} PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; } pcie_rp_aspm[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */ /* PCIe RP L1 substate */
enum { enum {