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soc/intel/alderlake: Implement API to disable UFS controllers 

This patch implements a new API to make the UFS controller function
disabled. Additionally, perform a warm reset post disabling the UFS
controller to let PMC know about the state of the UFS controller
and disable the MPHY clock.

BUG=b:264838335
TEST=Able to build and boot Google/Marasov successfully.
From the AP log, I am able to confirm that UFS is function disabled
using PSF.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I940a634f70f8c97ef1234866d4c5a1ff224c6e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Subrata Banik 2023-01-16 17:04:09 +05:30 committed by Lean Sheng Tan
parent 76d49a7c45
commit b53e27bc24
1 changed files with 30 additions and 0 deletions
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30
src/soc/intel/alderlake/romstage/romstage.c
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@ -2,11 +2,13 @@
#include <arch/romstage.h> #include <arch/romstage.h>
#include <cbmem.h> #include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/early_graphics.h> #include <intelblocks/early_graphics.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h> #include <intelblocks/smbus.h>
#include <intelblocks/thermal.h> #include <intelblocks/thermal.h>
@ -21,6 +23,23 @@
#include <timestamp.h> #include <timestamp.h>
#include <string.h> #include <string.h>
#include <security/intel/txt/txt.h> #include <security/intel/txt/txt.h>
#include <soc/pcr_ids.h>
#define PSF_UFS0_BASE_ADDRESS 0x280
#define PSF_UFS1_BASE_ADDRESS 0x300
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
static void disable_ufs(void)
{
/* disable USF0 */
pcr_or32(PID_PSF2, PSF_UFS0_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
/* disable USF1 */
pcr_or32(PID_PSF2, PSF_UFS1_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN,
PCR_PSFX_T0_SHDW_PCIEN_FUNDIS);
}
#include "ux.h" #include "ux.h"
@ -164,6 +183,17 @@ void mainboard_romstage_entry(void)
timestamp_add_now(TS_CSE_FW_SYNC_END); timestamp_add_now(TS_CSE_FW_SYNC_END);
} }
/* Program to Disable UFS Controllers */
if (!is_devfn_enabled(PCH_DEVFN_UFS) &&
(CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
printk(BIOS_INFO, "Disabling UFS controllers\n");
disable_ufs();
if (ps->prev_sleep_state == ACPI_S5) {
printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
system_reset();
}
}
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init(); systemagent_early_init();
/* Program SMBus base address and enable it */ /* Program SMBus base address and enable it */