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Need to clear downstream read cycle retry bit, or the bus scan will 

hang.  Also need to set lane config to 0x00 for autonegotiation.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Tobias Diedrich 2010-11-02 21:24:29 +00:00 committed by Rudolf Marek
parent d50b43a128
commit b54585244b
1 changed files with 35 additions and 2 deletions
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37
src/southbridge/via/k8t890/k8t890_pcie.c
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@ -35,7 +35,23 @@ static void peg_init(struct device *dev)
reg = pci_read_config8(dev, 0x50); reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10); pci_write_config8(dev, 0x50, reg | 0x10);
/* Award has 0xb, VIA recomends 0x4. */ /* Disable downstream read cycle retry,
* otherwise the bus scan will hang if no device is plugged in. */
reg = pci_read_config8(dev, 0xa3);
pci_write_config8(dev, 0xa3, reg & ~0x01);
/* Use PHY negotiation for lane config */
reg = pci_read_config8(dev, 0xc1);
pci_write_config8(dev, 0xc1, reg & ~0x1f);
/* Award has 0xb, VIA recommends 0xd, default 0x8.
* bit4: receive polarity change control
* bits3:2: squelch window select 64~175mv
* bit1: Number of non-idle bits detected before exiting idle state
* 0: 10 bits, 1: 2 bits
* bit0: Number of idle bits detected before entering idle state
* 0: 10 bits, 1: 2 bits
*/
pci_write_config8(dev, 0xe1, 0xb); pci_write_config8(dev, 0xe1, 0xb);
/* /*
@ -75,8 +91,25 @@ static void pcie_init(struct device *dev)
reg = pci_read_config8(dev, 0x50); reg = pci_read_config8(dev, 0x50);
pci_write_config8(dev, 0x50, reg | 0x10); pci_write_config8(dev, 0x50, reg | 0x10);
/* Award has 0xb, VIA recommends 0x4. */ /* Disable downstream read cycle retry,
* otherwise the bus scan will hang if no device is plugged in. */
reg = pci_read_config8(dev, 0xa3);
pci_write_config8(dev, 0xa3, reg & ~0x01);
/* Use PHY negotiation for lane config */
reg = pci_read_config8(dev, 0xc1);
pci_write_config8(dev, 0xc1, reg & ~0x1f);
/* Award has 0xb, VIA recommends 0xd, default 0x8.
* bit4: receive polarity change control
* bits3:2: squelch window select 64~175mv
* bit1: Number of non-idle bits detected before exiting idle state
* 0: 10 bits, 1: 2 bits
* bit0: Number of idle bits detected before entering idle state
* 0: 10 bits, 1: 2 bits
*/
pci_write_config8(dev, 0xe1, 0xb); pci_write_config8(dev, 0xe1, 0xb);
/* Set replay timer limit. */ /* Set replay timer limit. */
pci_write_config8(dev, 0xb1, 0xf0); pci_write_config8(dev, 0xb1, 0xf0);