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soc/intel/skylake: Support PL1 override option 

In legacy mode, DPTF on some systems may rely on MMIO to control PL1
settings. However, MSR PL1 also contributes to the decision of max
PL1 power; and in the current design, the lower value takes effect.
In order to align MMIO and MSR settings, a tdp_pl1_override option is
added to override the MSR PL1 limitation.

BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
     2. Verify the MSR PL1 limitation is set correctly.

Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Wei Shun Chang 2018-04-09 11:46:43 +08:00 committed by Patrick Georgi
parent 5d790e3f52
commit b54d15487a
2 changed files with 6 additions and 2 deletions
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2
src/soc/intel/skylake/chip.h
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@ -99,6 +99,8 @@ struct soc_intel_skylake_config {
/* PL2 Override value in Watts */
u32 tdp_pl2_override;
/* PL1 Override value in Watts */
u32 tdp_pl1_override;
/* SysPL2 Value in Watts */
u32 tdp_psyspl2;

6
src/soc/intel/skylake/cpu.c
View File

@ -117,7 +117,7 @@ void set_power_limits(u8 power_limit_1_time)
msr_t msr = rdmsr(MSR_PLATFORM_INFO);
msr_t limit;
unsigned int power_unit;
unsigned int tdp, min_power, max_power, max_time, tdp_pl2;
unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
u8 power_limit_1_val;
struct device *dev = SA_DEV_ROOT;
config_t *conf = dev->chip_info;
@ -154,7 +154,9 @@ void set_power_limits(u8 power_limit_1_time)
/* Set long term power limit to TDP */
limit.lo = 0;
limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
tdp_pl1 = ((conf->tdp_pl1_override == 0) ?
tdp : (conf->tdp_pl1_override * power_unit));
limit.lo |= (tdp_pl1 & PKG_POWER_LIMIT_MASK);
/* Set PL1 Pkg Power clamp bit */
limit.lo |= PKG_POWER_LIMIT_CLAMP;