diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index 7e27d89d70..1a23a9019a 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -17,6 +17,29 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 config CHROMEOS
 	select LID_SWITCH
 
+choice
+	prompt "TPM to USE"
+	default KBLRVP_TPM1_2
+	help
+	  This option allows you to select the TPM to use.
+	  Select whether the board does not have TPM, TPM 1.1 or TPM 2.0
+
+config KBLRVP_NO_TPM
+	bool "No TPM"
+	select VBOOT_MOCK_SECDATA if VBOOT
+
+config KBLRVP_TPM1_2
+	bool "TPM 1.1"
+	select MAINBOARD_HAS_LPC_TPM
+
+config KBLRVP_TPM2_0
+	bool "TPM 2.0"
+	select TPM2
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_LPC_TPM
+
+endchoice
+
 config DRIVERS_GENERIC_MAX98357A
 	default y
 
diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb
index 104a454963..11d5062664 100644
--- a/src/mainboard/intel/kblrvp/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/devicetree.cb
@@ -247,7 +247,11 @@ chip soc/intel/skylake
 		device pci 1e.4 on  end # eMMC
 		device pci 1e.5 off end # SDIO
 		device pci 1e.6 on  end # SDCard
-		device pci 1f.0 on  end # LPC Interface
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Interface
 		device pci 1f.1 on  end # P2SB
 		device pci 1f.2 on  end # Power Management Controller
 		device pci 1f.3 on  end # Intel HDA
diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h
index 01897a1a01..c6f41234ef 100644
--- a/src/mainboard/intel/kblrvp/gpio.h
+++ b/src/mainboard/intel/kblrvp/gpio.h
@@ -51,7 +51,7 @@ static const struct pad_config gpio_table[] = {
 /* PM_SLP_S0ix_N */	PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
 /* LPC_CLKRUN */	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
 /* LPC_CLK */		PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1),
-/* PCH_LPC_CLK */	PAD_CFG_NC(GPP_A10),
+/* PCH_LPC_CLK */	PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1),
 /* EC_HID_INT */	PAD_CFG_NC(GPP_A11),
 /* ISH_KB_PROX_INT */	PAD_CFG_NC(GPP_A12),
 /* PCH_SUSPWRACB */	PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),