mainboard: Add Lenovo ThinkPad T440p
The code is based on autoport. This port is tested on a T440p without a dGPU and can boot Arch Linux from SATA disk with SeaBIOS payload. The tested components and issues are in the documentation. Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Iru Cai
Patrick Georgi
parent
eef992deac
commit
b559432604
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@ -91,6 +91,10 @@ The boards in this section are not real mainboards, but emulators.
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- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
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- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
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- [T431s](lenovo/t431s.md)
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- [T431s](lenovo/t431s.md)
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### Haswell series
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- [T440p](lenovo/t440p.md)
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## Portwell
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## Portwell
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- [PQ7-M107](portwell/pq7-m107.md)
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- [PQ7-M107](portwell/pq7-m107.md)
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@ -0,0 +1,66 @@
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# Lenovo ThinkPad T440p
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This page describes how to run coreboot on [Lenovo ThinkPad T440p].
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## Required proprietary blobs
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Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).
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## Flashing instructions
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T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash
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coreboot, you just need to remove the big door according to the T440
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[Hardware Maintenance Manual] and flash the 4MB chip.
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To access the 8MB chip, you need to remove the base cover.
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The flash layout of the OEM firmware is as follows:
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00000000:00000fff fd
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00001000:00002fff gbe
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00003000:004fffff me
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00500000:00bfffff bios
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After flashing coreboot, you may need to re-plug the AC adapter to make
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the laptop able to power on.
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## Known Issues
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- No audio output when using a headphone
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- The touchpad is misconfigured, the 3 keys on top are all identified
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as left button
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- Cannot get the mainboard serial number from the mainboard: the OEM
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UEFI firmware gets the serial number from an "emulated EEPROM" via
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I/O port 0x1630/0x1634, but it's still unknown how to make it work
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## Untested
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- the dGPU model
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## Working
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- boot Arch Linux with Linux 4.19.77 from SeaBIOS payload
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- integrated graphics init with libgfxinit
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- EHCI debug: the port is the non-charging USB2 port on the right
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- video output: internal (eDP), miniDP, dock DP, dock HDMI
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- ACPI support
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- keyboard and trackpoint
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- SATA
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- M.2 SATA SSD
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- USB
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- Ethernet
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- WLAN
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- WWAN
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- bluetooth
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- virtualization: VT-x and VT-d
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- dock
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- CMOS options: wlan, trackpoint, fn_ctrl_swap
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- internal flashing when IFD is unlocked
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- using `me_cleaner`
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[Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p
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[Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf
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Binary file not shown.
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After Width: | Height: | Size: 82 KiB |
Binary file not shown.
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After Width: | Height: | Size: 80 KiB |
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@ -0,0 +1,54 @@
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if BOARD_LENOVO_THINKPAD_T440P
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_12288
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select CPU_INTEL_HASWELL
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select EC_LENOVO_H8
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select H8_HAS_PRIMARY_FN_KEYS
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select EC_LENOVO_PMH7
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select NO_UART_ON_SUPERIO
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select INTEL_GMA_HAVE_VBT
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select INTEL_INT15
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select MAINBOARD_HAS_LIBGFXINIT
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select NORTHBRIDGE_INTEL_HASWELL
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_LYNXPOINT
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select SYSTEM_TYPE_LAPTOP
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select MAINBOARD_USES_IFD_GBE_REGION
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config MAINBOARD_DIR
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string
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default lenovo/t440p
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config MAINBOARD_PART_NUMBER
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string
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default "ThinkPad T440p"
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config VGA_BIOS_FILE
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string
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default "pci8086,0416.rom"
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config VGA_BIOS_ID
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string
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default "8086,0416"
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 2
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config DRIVER_LENOVO_SERIALS
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bool
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default n
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endif
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@ -0,0 +1,2 @@
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config BOARD_LENOVO_THINKPAD_T440P
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bool "ThinkPad T440p"
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@ -0,0 +1,3 @@
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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smm-y += smihandler.c
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@ -0,0 +1,17 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <ec/lenovo/h8/acpi/ec.asl>
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Method(_WAK,1)
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{
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/* ME may not be up yet. */
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Store (0, \_TZ.MEB1)
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Store (0, \_TZ.MEB2)
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Return(Package(){0,0})
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}
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Method(_PTS,1)
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{
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\_SB.PCI0.LPCB.EC.RADI(0)
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}
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@ -0,0 +1,17 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Iru Cai <mytbk920423@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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@ -0,0 +1,35 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/lynxpoint/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* the lid is open by default */
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gnvs->lids = 1;
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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Category: laptop
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Board URL: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Release year: 2013
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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volume=0x3
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first_battery=Primary
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wlan=Enable
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fn_ctrl_swap=Disable
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f1_to_f12_as_primary=Enable
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sticky_fn=Disable
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trackpoint=Enable
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backlight=Both
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usb_always_on=Disable
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@ -0,0 +1,120 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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#400 8 r 0 reserved for century byte
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: EC
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411 1 e 8 first_battery
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415 1 e 1 wlan
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416 1 e 1 trackpoint
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417 1 e 1 fn_ctrl_swap
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418 1 e 1 sticky_fn
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419 2 e 13 usb_always_on
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422 2 e 10 backlight
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424 1 e 1 f1_to_f12_as_primary
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# coreboot config options: northbridge
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#435 2 e 12 hybrid_graphics_mode
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#437 3 r 0 unused
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440 8 h 0 volume
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# coreboot config options: check sums
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984 16 h 0 check_sum
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||||||
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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||||||
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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||||||
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6 1 Alert
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6 2 Critical
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6 3 Error
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||||||
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 Secondary
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||||||
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8 1 Primary
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9 0 AHCI
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9 1 Compatible
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10 0 Both
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10 1 Keyboard only
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10 2 Thinklight only
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10 3 None
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#12 0 Integrated Only
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#12 1 Discrete Only
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#12 2 Dual Graphics
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13 0 Disable
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13 1 AC and battery
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13 2 AC only
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||||||
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||||||
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# -----------------------------------------------------------------
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checksums
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checksum 392 447 984
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||||||
Binary file not shown.
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|
@ -0,0 +1,113 @@
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chip northbridge/intel/haswell
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
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||||||
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register "gfx.ndid" = "3"
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||||||
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register "gpu_cpu_backlight" = "0x12ba12ba"
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register "gpu_ddi_e_connected" = "1"
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||||||
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register "gpu_dp_b_hotplug" = "4"
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||||||
|
register "gpu_dp_c_hotplug" = "4"
|
||||||
|
register "gpu_dp_d_hotplug" = "4"
|
||||||
|
register "gpu_panel_port_select" = "0"
|
||||||
|
register "gpu_panel_power_backlight_off_delay" = "1"
|
||||||
|
register "gpu_panel_power_backlight_on_delay" = "1"
|
||||||
|
register "gpu_panel_power_cycle_delay" = "6"
|
||||||
|
register "gpu_panel_power_down_delay" = "500"
|
||||||
|
register "gpu_panel_power_up_delay" = "2000"
|
||||||
|
register "gpu_pch_backlight" = "0x12ba12ba"
|
||||||
|
device cpu_cluster 0x0 on
|
||||||
|
chip cpu/intel/haswell
|
||||||
|
register "c1_acpower" = "1"
|
||||||
|
register "c1_battery" = "1"
|
||||||
|
register "c2_acpower" = "3"
|
||||||
|
register "c2_battery" = "3"
|
||||||
|
register "c3_acpower" = "5"
|
||||||
|
register "c3_battery" = "5"
|
||||||
|
device lapic 0x0 on end
|
||||||
|
device lapic 0xacac off end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device domain 0x0 on
|
||||||
|
subsystemid 0x17aa 0x220e inherit
|
||||||
|
|
||||||
|
device pci 00.0 on end # Host bridge Host bridge
|
||||||
|
device pci 01.0 on end # PCIe Bridge for discrete graphics
|
||||||
|
device pci 02.0 on end # Internal graphics VGA controller
|
||||||
|
device pci 03.0 on end # Mini-HD audio Audio controller
|
||||||
|
|
||||||
|
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
|
||||||
|
register "gen1_dec" = "0x007c1601"
|
||||||
|
register "gen2_dec" = "0x000c15e1"
|
||||||
|
register "gen4_dec" = "0x000c06a1"
|
||||||
|
register "gpi13_routing" = "2"
|
||||||
|
register "gpi1_routing" = "2"
|
||||||
|
register "pirqa_routing" = "0x8b"
|
||||||
|
register "pirqb_routing" = "0x8a"
|
||||||
|
register "pirqc_routing" = "0x8a"
|
||||||
|
register "pirqd_routing" = "0x89"
|
||||||
|
register "pirqe_routing" = "0x86"
|
||||||
|
register "pirqf_routing" = "0x80"
|
||||||
|
register "pirqg_routing" = "0x8b"
|
||||||
|
register "pirqh_routing" = "0x87"
|
||||||
|
register "sata_ahci" = "1"
|
||||||
|
# 0(HDD), 1(M.2), 5(ODD)
|
||||||
|
register "sata_port_map" = "0x23"
|
||||||
|
device pci 14.0 on end # xHCI Controller
|
||||||
|
device pci 16.0 on end # Management Engine Interface 1
|
||||||
|
device pci 16.1 off end # Management Engine Interface 2
|
||||||
|
device pci 16.2 off end # Management Engine IDE-R
|
||||||
|
device pci 16.3 off end # Management Engine KT
|
||||||
|
device pci 19.0 on end # Intel Gigabit Ethernet
|
||||||
|
device pci 1a.0 on end # USB2 EHCI #2
|
||||||
|
device pci 1b.0 on end # High Definition Audio Audio controller
|
||||||
|
device pci 1c.0 on end # PCIe Port #1, Realtek Card Reader
|
||||||
|
device pci 1c.1 on # PCIe Port #2, WLAN
|
||||||
|
smbios_slot_desc "0x14" "1" "M.2 2230" "8"
|
||||||
|
end
|
||||||
|
device pci 1c.2 off end # PCIe Port #3
|
||||||
|
device pci 1c.3 off end # PCIe Port #4
|
||||||
|
device pci 1c.4 off end # PCIe Port #5
|
||||||
|
device pci 1c.5 off end # PCIe Port #6
|
||||||
|
device pci 1c.6 off end # PCIe Port #7
|
||||||
|
device pci 1c.7 off end # PCIe Port #8
|
||||||
|
device pci 1d.0 on end # USB2 EHCI #1
|
||||||
|
device pci 1f.0 on # LPC bridge PCI-LPC bridge
|
||||||
|
chip ec/lenovo/pmh7
|
||||||
|
register "backlight_enable" = "0x01"
|
||||||
|
register "dock_event_enable" = "0x01"
|
||||||
|
device pnp ff.1 on # dummy
|
||||||
|
end
|
||||||
|
end
|
||||||
|
chip ec/lenovo/h8
|
||||||
|
register "beepmask0" = "0x00"
|
||||||
|
register "beepmask1" = "0x86"
|
||||||
|
register "config0" = "0xa6"
|
||||||
|
register "config1" = "0x0d"
|
||||||
|
register "config2" = "0xa8"
|
||||||
|
register "config3" = "0xc4"
|
||||||
|
register "event2_enable" = "0xff"
|
||||||
|
register "event3_enable" = "0xff"
|
||||||
|
register "event4_enable" = "0xd0"
|
||||||
|
register "event5_enable" = "0x3c"
|
||||||
|
register "event7_enable" = "0x01"
|
||||||
|
register "event8_enable" = "0x7b"
|
||||||
|
register "event9_enable" = "0xff"
|
||||||
|
register "eventc_enable" = "0xff"
|
||||||
|
register "eventd_enable" = "0xff"
|
||||||
|
register "evente_enable" = "0x9d"
|
||||||
|
device pnp ff.2 on # dummy
|
||||||
|
io 0x60 = 0x62
|
||||||
|
io 0x62 = 0x66
|
||||||
|
io 0x64 = 0x1600
|
||||||
|
io 0x66 = 0x1604
|
||||||
|
end
|
||||||
|
end
|
||||||
|
chip drivers/pc80/tpm
|
||||||
|
device pnp 0c31.0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device pci 1f.2 on end # SATA Controller 1
|
||||||
|
device pci 1f.3 on end # SMBus
|
||||||
|
device pci 1f.5 off end # SATA Controller 2
|
||||||
|
device pci 1f.6 off end # Thermal
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
@ -0,0 +1,46 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2019 Iru Cai <mytbk920423@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||||
|
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||||
|
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||||
|
#define EC_LENOVO_H8_ME_WORKAROUND 1
|
||||||
|
#define THINKPAD_EC_GPE 17
|
||||||
|
|
||||||
|
#include <arch/acpi.h>
|
||||||
|
DefinitionBlock(
|
||||||
|
"dsdt.aml",
|
||||||
|
"DSDT",
|
||||||
|
0x02, // DSDT revision: ACPI 2.0 and up
|
||||||
|
OEM_ID,
|
||||||
|
ACPI_TABLE_CREATOR,
|
||||||
|
0x20141018 // OEM revision
|
||||||
|
)
|
||||||
|
{
|
||||||
|
#include "acpi/platform.asl"
|
||||||
|
#include <cpu/intel/common/acpi/cpu.asl>
|
||||||
|
#include <southbridge/intel/lynxpoint/acpi/platform.asl>
|
||||||
|
/* global NVS and variables. */
|
||||||
|
#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
|
||||||
|
#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
|
||||||
|
|
||||||
|
Device (\_SB.PCI0)
|
||||||
|
{
|
||||||
|
#include <northbridge/intel/haswell/acpi/haswell.asl>
|
||||||
|
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||||
|
#include <southbridge/intel/lynxpoint/acpi/pch.asl>
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
--
|
||||||
|
-- This file is part of the coreboot project.
|
||||||
|
--
|
||||||
|
-- This program is free software; you can redistribute it and/or modify
|
||||||
|
-- it under the terms of the GNU General Public License as published by
|
||||||
|
-- the Free Software Foundation; either version 2 of the License, or
|
||||||
|
-- (at your option) any later version.
|
||||||
|
--
|
||||||
|
-- This program is distributed in the hope that it will be useful,
|
||||||
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
-- GNU General Public License for more details.
|
||||||
|
--
|
||||||
|
|
||||||
|
with HW.GFX.GMA;
|
||||||
|
with HW.GFX.GMA.Display_Probing;
|
||||||
|
|
||||||
|
use HW.GFX.GMA;
|
||||||
|
use HW.GFX.GMA.Display_Probing;
|
||||||
|
|
||||||
|
private package GMA.Mainboard is
|
||||||
|
|
||||||
|
ports : constant Port_List :=
|
||||||
|
(DP1, -- MiniDP
|
||||||
|
DP2, -- dock, DP2-1 (DP/HDMI) and DP2-2 (DP/DVI)
|
||||||
|
Analog,
|
||||||
|
Internal,
|
||||||
|
others => Disabled);
|
||||||
|
|
||||||
|
end GMA.Mainboard;
|
||||||
|
|
@ -0,0 +1,224 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2014 Vladimir Serbinenko
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <southbridge/intel/common/gpio.h>
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||||
|
.gpio0 = GPIO_MODE_GPIO,
|
||||||
|
.gpio1 = GPIO_MODE_GPIO,
|
||||||
|
.gpio2 = GPIO_MODE_GPIO,
|
||||||
|
.gpio3 = GPIO_MODE_GPIO,
|
||||||
|
.gpio4 = GPIO_MODE_GPIO,
|
||||||
|
.gpio5 = GPIO_MODE_GPIO,
|
||||||
|
.gpio6 = GPIO_MODE_GPIO,
|
||||||
|
.gpio7 = GPIO_MODE_GPIO,
|
||||||
|
.gpio8 = GPIO_MODE_GPIO,
|
||||||
|
.gpio9 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio10 = GPIO_MODE_GPIO,
|
||||||
|
.gpio11 = GPIO_MODE_GPIO,
|
||||||
|
.gpio12 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio13 = GPIO_MODE_GPIO,
|
||||||
|
.gpio14 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio15 = GPIO_MODE_GPIO,
|
||||||
|
.gpio16 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio17 = GPIO_MODE_GPIO,
|
||||||
|
.gpio18 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio19 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio20 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio21 = GPIO_MODE_GPIO,
|
||||||
|
.gpio22 = GPIO_MODE_GPIO,
|
||||||
|
.gpio23 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio24 = GPIO_MODE_GPIO,
|
||||||
|
.gpio25 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio26 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio27 = GPIO_MODE_GPIO,
|
||||||
|
.gpio28 = GPIO_MODE_GPIO,
|
||||||
|
.gpio29 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio30 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio31 = GPIO_MODE_GPIO,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||||
|
.gpio0 = GPIO_DIR_INPUT,
|
||||||
|
.gpio1 = GPIO_DIR_INPUT,
|
||||||
|
.gpio2 = GPIO_DIR_INPUT,
|
||||||
|
.gpio3 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio4 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio5 = GPIO_DIR_INPUT,
|
||||||
|
.gpio6 = GPIO_DIR_INPUT,
|
||||||
|
.gpio7 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio8 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio10 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio11 = GPIO_DIR_INPUT,
|
||||||
|
.gpio13 = GPIO_DIR_INPUT,
|
||||||
|
.gpio15 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio17 = GPIO_DIR_INPUT,
|
||||||
|
.gpio21 = GPIO_DIR_INPUT,
|
||||||
|
.gpio22 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio24 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio27 = GPIO_DIR_INPUT,
|
||||||
|
.gpio28 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio31 = GPIO_DIR_INPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||||
|
.gpio3 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio4 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio7 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio8 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio10 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio15 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio22 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio24 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio28 = GPIO_LEVEL_LOW,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||||
|
.gpio24 = GPIO_RESET_RSMRST,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||||
|
.gpio0 = GPIO_INVERT,
|
||||||
|
.gpio1 = GPIO_INVERT,
|
||||||
|
.gpio11 = GPIO_INVERT,
|
||||||
|
.gpio13 = GPIO_INVERT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||||
|
.gpio32 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio33 = GPIO_MODE_GPIO,
|
||||||
|
.gpio34 = GPIO_MODE_GPIO,
|
||||||
|
.gpio35 = GPIO_MODE_GPIO,
|
||||||
|
.gpio36 = GPIO_MODE_GPIO,
|
||||||
|
.gpio37 = GPIO_MODE_GPIO,
|
||||||
|
.gpio38 = GPIO_MODE_GPIO,
|
||||||
|
.gpio39 = GPIO_MODE_GPIO,
|
||||||
|
.gpio40 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio41 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio42 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio43 = GPIO_MODE_GPIO,
|
||||||
|
.gpio44 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio45 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio46 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio47 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio48 = GPIO_MODE_GPIO,
|
||||||
|
.gpio49 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio50 = GPIO_MODE_GPIO,
|
||||||
|
.gpio51 = GPIO_MODE_GPIO,
|
||||||
|
.gpio52 = GPIO_MODE_GPIO,
|
||||||
|
.gpio53 = GPIO_MODE_GPIO,
|
||||||
|
.gpio54 = GPIO_MODE_GPIO,
|
||||||
|
.gpio55 = GPIO_MODE_GPIO,
|
||||||
|
.gpio56 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio57 = GPIO_MODE_GPIO,
|
||||||
|
.gpio58 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio59 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio60 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio61 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio62 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio63 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||||
|
.gpio33 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio34 = GPIO_DIR_INPUT,
|
||||||
|
.gpio35 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio36 = GPIO_DIR_INPUT,
|
||||||
|
.gpio37 = GPIO_DIR_INPUT,
|
||||||
|
.gpio38 = GPIO_DIR_INPUT,
|
||||||
|
.gpio39 = GPIO_DIR_INPUT,
|
||||||
|
.gpio43 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio48 = GPIO_DIR_INPUT,
|
||||||
|
.gpio50 = GPIO_DIR_INPUT,
|
||||||
|
.gpio51 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio52 = GPIO_DIR_INPUT,
|
||||||
|
.gpio53 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio54 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio55 = GPIO_DIR_OUTPUT,
|
||||||
|
.gpio57 = GPIO_DIR_INPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||||
|
.gpio33 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio35 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio43 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio51 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio53 = GPIO_LEVEL_HIGH,
|
||||||
|
.gpio54 = GPIO_LEVEL_LOW,
|
||||||
|
.gpio55 = GPIO_LEVEL_HIGH,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||||
|
.gpio64 = GPIO_MODE_GPIO,
|
||||||
|
.gpio65 = GPIO_MODE_GPIO,
|
||||||
|
.gpio66 = GPIO_MODE_GPIO,
|
||||||
|
.gpio67 = GPIO_MODE_GPIO,
|
||||||
|
.gpio68 = GPIO_MODE_GPIO,
|
||||||
|
.gpio69 = GPIO_MODE_GPIO,
|
||||||
|
.gpio70 = GPIO_MODE_GPIO,
|
||||||
|
.gpio71 = GPIO_MODE_GPIO,
|
||||||
|
.gpio72 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio73 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio74 = GPIO_MODE_NATIVE,
|
||||||
|
.gpio75 = GPIO_MODE_NATIVE,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||||
|
.gpio64 = GPIO_DIR_INPUT,
|
||||||
|
.gpio65 = GPIO_DIR_INPUT,
|
||||||
|
.gpio66 = GPIO_DIR_INPUT,
|
||||||
|
.gpio67 = GPIO_DIR_INPUT,
|
||||||
|
.gpio68 = GPIO_DIR_INPUT,
|
||||||
|
.gpio69 = GPIO_DIR_INPUT,
|
||||||
|
.gpio70 = GPIO_DIR_INPUT,
|
||||||
|
.gpio71 = GPIO_DIR_INPUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct pch_gpio_map mainboard_gpio_map = {
|
||||||
|
.set1 = {
|
||||||
|
.mode = &pch_gpio_set1_mode,
|
||||||
|
.direction = &pch_gpio_set1_direction,
|
||||||
|
.level = &pch_gpio_set1_level,
|
||||||
|
.blink = &pch_gpio_set1_blink,
|
||||||
|
.invert = &pch_gpio_set1_invert,
|
||||||
|
.reset = &pch_gpio_set1_reset,
|
||||||
|
},
|
||||||
|
.set2 = {
|
||||||
|
.mode = &pch_gpio_set2_mode,
|
||||||
|
.direction = &pch_gpio_set2_direction,
|
||||||
|
.level = &pch_gpio_set2_level,
|
||||||
|
.reset = &pch_gpio_set2_reset,
|
||||||
|
},
|
||||||
|
.set3 = {
|
||||||
|
.mode = &pch_gpio_set3_mode,
|
||||||
|
.direction = &pch_gpio_set3_direction,
|
||||||
|
.level = &pch_gpio_set3_level,
|
||||||
|
.reset = &pch_gpio_set3_reset,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2014 Vladimir Serbinenko
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/azalia_device.h>
|
||||||
|
|
||||||
|
const u32 cim_verb_data[] = {
|
||||||
|
0x10ec0292, /* Codec Vendor / Device ID: Realtek */
|
||||||
|
0x17aa220e, /* Subsystem ID */
|
||||||
|
12, /* Number of 4 dword sets */
|
||||||
|
AZALIA_SUBVENDOR(0x0, 0x17aa220e),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x13, 0x40000000),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x15, 0x0321101f),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1a, 0x03a11020),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1d, 0x40738105),
|
||||||
|
AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
|
||||||
|
};
|
||||||
|
|
||||||
|
const u32 pc_beep_verbs[0] = {};
|
||||||
|
|
||||||
|
AZALIA_ARRAY_SIZES;
|
||||||
|
|
@ -0,0 +1,34 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2019 Iru Cai <mytbk920423@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <drivers/intel/gma/int15.h>
|
||||||
|
#include <ec/lenovo/h8/h8.h>
|
||||||
|
|
||||||
|
static void mainboard_enable(struct device *dev)
|
||||||
|
{
|
||||||
|
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
|
||||||
|
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||||
|
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void h8_mainboard_init_dock(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations mainboard_ops = {
|
||||||
|
.enable_dev = mainboard_enable,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,103 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2014 Vladimir Serbinenko
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <arch/romstage.h>
|
||||||
|
#include <cpu/intel/haswell/haswell.h>
|
||||||
|
#include <northbridge/intel/haswell/haswell.h>
|
||||||
|
#include <northbridge/intel/haswell/pei_data.h>
|
||||||
|
#include <southbridge/intel/common/gpio.h>
|
||||||
|
#include <southbridge/intel/lynxpoint/pch.h>
|
||||||
|
|
||||||
|
static const struct rcba_config_instruction rcba_config[] = {
|
||||||
|
RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)),
|
||||||
|
RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)),
|
||||||
|
RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),
|
||||||
|
RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)),
|
||||||
|
RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)),
|
||||||
|
RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)),
|
||||||
|
RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||||
|
RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
|
||||||
|
|
||||||
|
RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS),
|
||||||
|
|
||||||
|
RCBA_END_CONFIG,
|
||||||
|
};
|
||||||
|
|
||||||
|
void mainboard_config_superio(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_romstage_entry(void)
|
||||||
|
{
|
||||||
|
struct pei_data pei_data = {
|
||||||
|
.pei_version = PEI_VERSION,
|
||||||
|
.mchbar = (uintptr_t)DEFAULT_MCHBAR,
|
||||||
|
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
|
||||||
|
.epbar = DEFAULT_EPBAR,
|
||||||
|
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
|
||||||
|
.smbusbar = SMBUS_IO_BASE,
|
||||||
|
.wdbbar = 0x4000000,
|
||||||
|
.wdbsize = 0x1000,
|
||||||
|
.hpet_address = HPET_ADDR,
|
||||||
|
.rcba = (uintptr_t)DEFAULT_RCBA,
|
||||||
|
.pmbase = DEFAULT_PMBASE,
|
||||||
|
.gpiobase = DEFAULT_GPIOBASE,
|
||||||
|
.temp_mmio_base = 0xfed08000,
|
||||||
|
.system_type = 0, /* mobile */
|
||||||
|
.tseg_size = CONFIG_SMM_TSEG_SIZE,
|
||||||
|
.spd_addresses = { 0xa0, 0, 0xa2, 0 },
|
||||||
|
.ec_present = 1,
|
||||||
|
.gbe_enable = 1,
|
||||||
|
.dimm_channel0_disabled = 2,
|
||||||
|
.dimm_channel1_disabled = 2,
|
||||||
|
.max_ddr3_freq = 1600,
|
||||||
|
.usb2_ports = {
|
||||||
|
/* Length, Enable, OCn#, Location */
|
||||||
|
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
|
||||||
|
{ 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* USB3 */
|
||||||
|
{ 0x0110, 1, 1, USB_PORT_BACK_PANEL }, /* USB2 charge */
|
||||||
|
{ 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL },
|
||||||
|
{ 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK },
|
||||||
|
{ 0x0080, 1, 2, USB_PORT_BACK_PANEL }, /* USB2 */
|
||||||
|
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
|
||||||
|
{ 0x0040, 1, 3, USB_PORT_BACK_PANEL },
|
||||||
|
{ 0x0040, 1, 4, USB_PORT_BACK_PANEL },
|
||||||
|
{ 0x0110, 1, 4, USB_PORT_BACK_PANEL }, /* WWAN */
|
||||||
|
{ 0x0040, 1, 5, USB_PORT_INTERNAL }, /* WLAN */
|
||||||
|
{ 0x0040, 1, 5, USB_PORT_BACK_PANEL }, /* webcam */
|
||||||
|
{ 0x0080, 1, 6, USB_PORT_BACK_PANEL },
|
||||||
|
{ 0x0040, 1, 6, USB_PORT_BACK_PANEL },
|
||||||
|
},
|
||||||
|
.usb3_ports = {
|
||||||
|
{ 1, 0 },
|
||||||
|
{ 1, 0 },
|
||||||
|
{ 1, USB_OC_PIN_SKIP },
|
||||||
|
{ 1, USB_OC_PIN_SKIP },
|
||||||
|
{ 1, 1 },
|
||||||
|
{ 1, 1 }, /* WWAN */
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
struct romstage_params romstage_params = {
|
||||||
|
.pei_data = &pei_data,
|
||||||
|
.gpio_map = &mainboard_gpio_map,
|
||||||
|
.rcba_config = rcba_config,
|
||||||
|
};
|
||||||
|
|
||||||
|
romstage_common(&romstage_params);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2014 Vladimir Serbinenko
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; version 2 of
|
||||||
|
* the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <cpu/x86/smm.h>
|
||||||
|
#include <ec/acpi/ec.h>
|
||||||
|
#include <ec/lenovo/h8/h8.h>
|
||||||
|
#include <delay.h>
|
||||||
|
#include <southbridge/intel/lynxpoint/pch.h>
|
||||||
|
|
||||||
|
#define GPE_EC_SCI 1
|
||||||
|
#define GPE_EC_WAKE 13
|
||||||
|
|
||||||
|
static void mainboard_smi_handle_ec_sci(void)
|
||||||
|
{
|
||||||
|
u8 status = inb(EC_SC);
|
||||||
|
u8 event;
|
||||||
|
|
||||||
|
if (!(status & EC_SCI_EVT))
|
||||||
|
return;
|
||||||
|
|
||||||
|
event = ec_query();
|
||||||
|
printk(BIOS_DEBUG, "EC event %02x\n", event);
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_smi_gpi(u32 gpi_sts)
|
||||||
|
{
|
||||||
|
if (gpi_sts & (1 << GPE_EC_SCI))
|
||||||
|
mainboard_smi_handle_ec_sci();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* lynxpoint doesn't have gpi_route_interrupt, so add it */
|
||||||
|
#define GPI_DISABLE 0x00
|
||||||
|
#define GPI_IS_SMI 0x01
|
||||||
|
#define GPI_IS_SCI 0x02
|
||||||
|
#define GPI_IS_NMI 0x03
|
||||||
|
|
||||||
|
static void gpi_route_interrupt(u8 gpi, u8 mode)
|
||||||
|
{
|
||||||
|
u32 gpi_rout;
|
||||||
|
|
||||||
|
gpi_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
|
||||||
|
gpi_rout &= ~(3 << (2 * gpi));
|
||||||
|
gpi_rout |= ((mode & 3) << (2 * gpi));
|
||||||
|
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpi_rout);
|
||||||
|
}
|
||||||
|
|
||||||
|
int mainboard_smi_apmc(u8 data)
|
||||||
|
{
|
||||||
|
switch (data) {
|
||||||
|
case APM_CNT_ACPI_ENABLE:
|
||||||
|
/* use 0x1600/0x1604 to prevent races with userspace */
|
||||||
|
ec_set_ports(0x1604, 0x1600);
|
||||||
|
/* route EC_SCI to SCI */
|
||||||
|
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
|
||||||
|
/* discard all events, and enable attention */
|
||||||
|
ec_write(0x80, 0x01);
|
||||||
|
break;
|
||||||
|
case APM_CNT_ACPI_DISABLE:
|
||||||
|
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
|
||||||
|
provide a EC query function */
|
||||||
|
ec_set_ports(0x66, 0x62);
|
||||||
|
/* route EC_SCI to SMI */
|
||||||
|
gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
|
||||||
|
/* discard all events, and enable attention */
|
||||||
|
ec_write(0x80, 0x01);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_smi_sleep(u8 slp_typ)
|
||||||
|
{
|
||||||
|
if (slp_typ == 3) {
|
||||||
|
u8 ec_wake = ec_read(0x32);
|
||||||
|
/* If EC wake events are enabled,
|
||||||
|
* enable wake on EC WAKE GPE. */
|
||||||
|
if (ec_wake & 0x14) {
|
||||||
|
/* Redirect EC WAKE GPE to SCI. */
|
||||||
|
gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue