nb/x4x: Use system_reset() and full_reset()
Use already defined system_reset() and full_reset() functions. Change-Id: I0a05f3ac5c5340a509024de2b444960f498c3e99 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -17,6 +17,7 @@
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <cf9_reset.h>
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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@ -654,13 +655,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
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if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) {
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if (boot_path == BOOT_PATH_RESUME) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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halt();
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system_reset();
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} else if (boot_path == BOOT_PATH_WARM_RESET) {
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/* On warm reset some of dram calibrations fail
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and therefore requiring valid cached settings */
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outb(0xe, 0xcf9);
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halt();
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full_reset();
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}
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ctrl_cached = NULL;
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} else {
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@ -728,8 +727,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
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&s, sizeof(s));
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if (s.boot_path == BOOT_PATH_RESUME && !cbmem_was_inited) {
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/* Failed S3 resume, reset to come up cleanly */
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outb(0x6, 0xcf9);
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halt();
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system_reset();
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}
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timestamp_add_now(TS_AFTER_INITRAM);
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