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for tyan. recover from Eric B's error additions to via code :-) 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2003-10-15 20:05:11 +00:00
parent 820dea8a62
commit b56ef07600
15 changed files with 198 additions and 64 deletions
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3
src/devices/pci_device.c
View File

@ -699,6 +699,8 @@ static void pci_level_irq(unsigned char intNum)
outb((unsigned char) intBits, 0x4d0);
outb((unsigned char) (intBits >> 8), 0x4d1);
/* this seems like an error but is not ... */
#if 0
if (inb(0x4d0) != (intBits & 0xf)) {
printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
__FUNCTION__, intBits &0xf, inb(0x4d0));
@ -707,6 +709,7 @@ static void pci_level_irq(unsigned char intNum)
printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
__FUNCTION__, (intBits>>8) &0xf, inb(0x4d1));
}
#endif
}
/*

22
src/mainboard/tyan/s2880/Config.lb
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@ -142,20 +142,24 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131"
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111"
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0
pci 0:1.1
pci 0:1.2
pci 0:1.3
pci 0:1.5
pci 0:1.6
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
end
end
@ -182,7 +186,7 @@ end
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
dir /bioscall
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"

8
src/mainboard/tyan/s2880/auto.c
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@ -15,6 +15,8 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define REV_B_RESET 0
static void memreset_setup(void)
@ -88,8 +90,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
#include "northbridge/amd/amdk8/cpu_ldtstop.c"
#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -162,7 +164,7 @@ static void main(void)
enable_lapic();
init_timer();
if (!boot_cpu() ) {
notify_bsp_ap_is_stopped();
// notify_bsp_ap_is_stopped();
stop_this_cpu();
}
uart_init();

23
src/mainboard/tyan/s2882/Config.lb
View File

@ -13,6 +13,7 @@ uses ARCH
###
### Build the objects we have code for in this directory.
###
##object mainboard.o
config chip.h
register "fixup_scsi" = "1"
register "fixup_vga" = "1"
@ -140,20 +141,24 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131"
southbridge amd/amd8131 "amd8131" link 0
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111"
southbridge amd/amd8111 "amd8111" link 0
pci 0:0.0
pci 0:1.0
pci 0:1.1
pci 0:1.2
pci 0:1.3
pci 0:1.5
pci 0:1.6
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 off
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
end
end
@ -179,7 +184,7 @@ end
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
dir /bioscall
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"

8
src/mainboard/tyan/s2882/auto.c
View File

@ -15,6 +15,8 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
static void memreset_setup(void)
{
@ -84,8 +86,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
#include "northbridge/amd/amdk8/cpu_ldtstop.c"
#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
@ -182,7 +184,7 @@ static void main(void)
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
#if 1
#if 0
dump_pci_devices();
#endif
#if 0

4
src/mainboard/tyan/s2882/mptable.c
View File

@ -88,7 +88,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
#endif
//Onboard SI Serial ATA
// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x14, 0x2, 0x11);
#if 0
#if 1
//Slot 3 PCIX 100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x20, 0x3, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x21, 0x3, 0x0);
@ -107,7 +107,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
//On Board NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x24, 0x3, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x25, 0x3, 0x1);
#if 0
#if 1
//Slot 1 PCI-X 133/100/66
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xc, 0x4, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, 0xd, 0x4, 0x1);

30
src/mainboard/tyan/s2885/Config.lb
View File

@ -13,6 +13,7 @@ uses ARCH
###
### Build the objects we have code for in this directory.
###
##object mainboard.o
config chip.h
register "fixup_scsi" = "1"
register "fixup_vga" = "1"
@ -141,24 +142,29 @@ northbridge amd/amdk8 "mc0"
pci 0:18.1
pci 0:18.2
pci 0:18.3
southbridge amd/amd8131 "amd8131"
southbridge amd/amd8131 "amd8131" link 2
pci 0:0.0
pci 0:0.1
pci 0:1.0
pci 0:1.1
end
southbridge amd/amd8111 "amd8111"
southbridge amd/amd8111 "amd8111" link 2
pci 0:0.0
pci 0:1.0
pci 0:1.1
pci 0:1.2
pci 0:1.3
pci 0:1.5
pci 0:1.6
pci 0:1.0 on
pci 0:1.1 on
pci 0:1.2 on
pci 0:1.3 on
pci 0:1.5 on
pci 0:1.6 off
pci 1:0.0 on
pci 1:0.1 on
pci 1:0.2 on
pci 1:1.0 off
end
southbridge amd/amd8151 "amd8151"
pci 2:0.0
pci 2:1.0
southbridge amd/amd8151 "amd8151" link 0
pci 0:0.0
pci 0:1.0
end
end
@ -187,7 +193,7 @@ end
#end
dir /pc80
##dir /src/superio/winbond/w83627hf
dir /bioscall
#dir /bioscall
#dir /cpu/k8
cpu k8 "cpu0"
register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"

5
src/mainboard/tyan/s2885/auto.c
View File

@ -16,6 +16,8 @@
#include "cpu/p6/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
#define REV_B_RESET 0
static void memreset_setup(void)
@ -89,9 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
#include "northbridge/amd/amdk8/cpu_ldtstop.c"
#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"

2
src/mainboard/tyan/s2885/resourcemap.c
View File

@ -254,6 +254,8 @@ static void setup_s2885_resource_map(void)
*/
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x04000203,
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x06050003,
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x00000203,
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
};

4
src/mainboard/via/epia/auto.c
View File

@ -26,8 +26,8 @@ void udelay(int usecs)
#include "southbridge/via/vt8231/vt8231_early_smbus.c"
#define MAXIMUM_CONSOLE_LOGLEVEL 9
#define DEFAULT_CONSOLE_LOGLEVEL 9
#define MAXIMUM_CONSOLE_LOGLEVEL 6
#define DEFAULT_CONSOLE_LOGLEVEL 6
#include "southbridge/via/vt8231/vt8231_early_serial.c"
static void memreset_setup(void)

22
targets/tyan/s2880/Config.lb
View File

@ -56,11 +56,11 @@ uses XIP_ROM_BASE
uses HAVE_HARD_RESET
uses CONFIG_VGABIOS
uses CONFIG_REALMODE_IDT
uses CONFIG_PCIBIOS
uses VGABIOS_START
uses SCSIFW_START
#uses CONFIG_VGABIOS
#uses CONFIG_REALMODE_IDT
#uses CONFIG_PCIBIOS
#uses VGABIOS_START
#uses SCSIFW_START
#
#uses CONFIG_LSI_SCSI_FW_FIXUP
@ -78,11 +78,11 @@ option k7=1
option k8=1
option ROM_SIZE=524288
option CONFIG_VGABIOS=0
option CONFIG_REALMODE_IDT=0
option CONFIG_PCIBIOS=0
option VGABIOS_START=0xfff8c000
option SCSIFW_START=0xfff80000
#option CONFIG_VGABIOS=0
#option CONFIG_REALMODE_IDT=0
#option CONFIG_PCIBIOS=0
#option VGABIOS_START=0xfff8c000
#option SCSIFW_START=0xfff80000
option HAVE_FALLBACK_BOOT=1
@ -236,4 +236,4 @@ romimage "fallback"
payload ../../tg3.zelf
end
buildrom ROM_SIZE "normal" "fallback"
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

2
targets/tyan/s2882/Config.lb
View File

@ -235,4 +235,4 @@ romimage "fallback"
payload ../../tg3.zelf
end
buildrom ROM_SIZE "normal" "fallback"
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

13
targets/tyan/s2885/Config.lb
View File

@ -41,7 +41,6 @@ uses USE_FALLBACK_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses CONFIG_CHIP_CONFIGURE
uses CONFIG_LEGACY_VGABIOS
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
@ -56,10 +55,10 @@ uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses HAVE_HARD_RESET
uses CONFIG_VGABIOS
uses CONFIG_REALMODE_IDT
uses CONFIG_PCIBIOS
uses VGABIOS_START
#uses CONFIG_VGABIOS
#uses CONFIG_REALMODE_IDT
#uses CONFIG_PCIBIOS
#uses VGABIOS_START
#uses SCSIFW_START
#
@ -76,7 +75,7 @@ option k7=1
option k8=1
option ROM_SIZE=524288
option CONFIG_LEGACY_VGABIOS=1
#option CONFIG_VGABIOS=1
#option CONFIG_REALMODE_IDT=1
#option CONFIG_PCIBIOS=1
#option VGABIOS_START=1
@ -235,4 +234,4 @@ romimage "fallback"
payload ../../tg3--ide_disk.zelf
end
buildrom ROM_SIZE "normal" "fallback"
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

109
targets/via/epia/Config.filo.lb Normal file
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@ -0,0 +1,109 @@
# Sample config file for Motorola Sandpoint X3 Demo Board with
# the Arima HDAMA
# This will make a target directory of ./hdama
loadoptions
target epia
uses ARCH
uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_KEYBOARD
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
uses FALLBACK_SIZE
uses HAVE_FALLBACK_BOOT
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_HARD_RESET
uses i586
uses i686
uses INTEL_PPRO_MTRR
uses HEAP_SIZE
uses IRQ_SLOT_COUNT
uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR
uses CONFIG_SMP
uses CONFIG_MAX_CPUS
uses MEMORY_HOLE
uses PAYLOAD_SIZE
uses _RAMBASE
uses _ROMBASE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_OFFSET
uses ROM_SECTION_SIZE
uses ROM_SIZE
uses STACK_SIZE
uses USE_FALLBACK_IMAGE
uses USE_OPTION_TABLE
uses HAVE_OPTION_TABLE
uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses MAINBOARD
uses CONFIG_CHIP_CONFIGURE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses LINUXBIOS_EXTRA_VERSION
option CONFIG_CHIP_CONFIGURE=1
option CONFIG_KEYBOARD=1
option MAXIMUM_CONSOLE_LOGLEVEL=10
option DEFAULT_CONSOLE_LOGLEVEL=10
option CONFIG_CONSOLE_SERIAL8250=1
option CPU_FIXUP=1
option CONFIG_UDELAY_TSC=0
option i686=1
option i586=1
option INTEL_PPRO_MTRR=1
option ROM_SIZE=256*1024
option HAVE_OPTION_TABLE=1
option CONFIG_ROM_STREAM=1
option HAVE_FALLBACK_BOOT=1
###
### Compute the location and size of where this firmware image
### (linuxBIOS plus bootloader) will live in the boot rom chip.
###
option FALLBACK_SIZE=131072
## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00004000
#
###
### Compute the start location and size size of
### The linuxBIOS bootloader.
###
#
# Arima hdama
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Normal"
mainboard via/epia
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
payload ../../../../../../filo.elf
end
romimage "fallback"
option USE_FALLBACK_IMAGE=1
option ROM_IMAGE_SIZE=0x10000
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
mainboard via/epia
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf
# payload ../../../../../lnxieepro100.ebi
payload ../../../../../../filo.elf
end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"

7
targets/via/epia/Config.lb
View File

@ -48,12 +48,15 @@ uses CONFIG_CHIP_CONFIGURE
uses XIP_ROM_SIZE
uses XIP_ROM_BASE
uses LINUXBIOS_EXTRA_VERSION
uses TTYS0_BAUD
option TTYS0_BAUD=19200
option CONFIG_CHIP_CONFIGURE=1
option CONFIG_KEYBOARD=1
option MAXIMUM_CONSOLE_LOGLEVEL=10
option DEFAULT_CONSOLE_LOGLEVEL=10
option MAXIMUM_CONSOLE_LOGLEVEL=7
option DEFAULT_CONSOLE_LOGLEVEL=7
option CONFIG_CONSOLE_SERIAL8250=1
option CPU_FIXUP=1