From b572c9d5e553c0cefc9d2f43c924430324a6eaaf Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 14 Oct 2019 18:18:46 +0200 Subject: [PATCH] nb/intel/nehalem: Add some debug output Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/northbridge/intel/nehalem/raminit.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 75be57231b..46189117a7 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3730,6 +3730,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap) int cbmem_wasnot_inited; x2ca8 = MCHBAR8(0x2ca8); + + printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); + deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -4241,6 +4244,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) if (x2ca8 == 0) { MCHBAR8_AND(0x2ca8, ~3); MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8) + 4; // "+" or "|"? + /* This issues a CPU reset without resetting the platform */ + printk(BIOS_DEBUG, "Issuing a CPU reset\n"); MCHBAR32_OR(0x1af0, 0x10); halt(); }