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vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3425 

Update FSP headers for Tiger Lake platform generated based on FSP
version 3425. Previous version was 3373.

BUG=b:172045149
BRANCH=none
TEST=build and boot delbin

Cq-Depend:chrome-internal:3373431
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I58d165d452c8c6ae2eec92524109a568f7e581a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47041
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-10-30 11:36:15 -07:00 committed by Furquan Shaikh
parent 184c794086
commit b57f22fc5b
1 changed files with 3 additions and 3 deletions
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6
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
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@ -2498,7 +2498,7 @@ typedef struct {
/** Offset 0x091C - Reserved /** Offset 0x091C - Reserved
**/ **/
UINT8 Reserved45[12]; UINT8 Reserved45[36];
} FSP_M_CONFIG; } FSP_M_CONFIG;
/** Fsp M UPD Configuration /** Fsp M UPD Configuration
@ -2517,11 +2517,11 @@ typedef struct {
**/ **/
FSP_M_CONFIG FspmConfig; FSP_M_CONFIG FspmConfig;
/** Offset 0x0928 /** Offset 0x0940
**/ **/
UINT8 UnusedUpdSpace27[6]; UINT8 UnusedUpdSpace27[6];
/** Offset 0x092E /** Offset 0x0946
**/ **/
UINT16 UpdTerminator; UINT16 UpdTerminator;
} FSPM_UPD; } FSPM_UPD;