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soc/intel/cannonlake: Add missing _PCH_DEV definitions 

Add all missing _PCH_DEV definitions to pci_devs.h

Change-Id: I0f2eec5dff000738f41cfa6aec11b54a65f8adc3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-08-09 09:38:45 -07:00 committed by Martin Roth
parent 285f9f2fe3
commit b58366a4c0
1 changed files with 21 additions and 6 deletions
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27
src/soc/intel/cannonlake/include/soc/pci_devs.h
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@ -50,12 +50,16 @@
/* PCH Devices */
#define PCH_DEV_SLOT_THERMAL 0x12
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)
#define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5)
#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6)
#define PCH_DEVFN_GSPI2 _PCH_DEVFN(THERMAL, 6)
#define PCH_DEV_THERMAL _PCH_DEV(THERMAL, 0)
#define PCH_DEV_UFS _PCH_DEV(THERMAL, 5)
#define PCH_DEV_GSPI2 _PCH_DEV(THERMAL, 6)
#define PCH_DEV_SLOT_ISH 0x13
#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)
#define PCH_DEV_ISH _PCH_DEV(ISH, 0)
#define PCH_DEV_SLOT_XHCI 0x14
#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
@ -65,7 +69,7 @@
#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1)
#define PCH_DEV_CNViWIFI _PCH_DEV(XHCI, 3)
#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
#define PCH_DEV_SLOT_SIO1 0x15
#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0)
@ -98,12 +102,14 @@
#define PCH_DEV_SLOT_SIO2 0x19
#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0)
#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1)
#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2)
#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2)
#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0)
#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1)
#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2)
#define PCH_DEV_SLOT_STORAGE 0x1A
#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)
#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)
#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0)
#define PCH_DEV_SLOT_PCIE 0x1c
#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)
@ -120,12 +126,18 @@
#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)
#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)
#define PCH_DEV_SLOT_PCIE_1 0x1d
#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
#define PCH_DEV_SLOT_SIO3 0x1e
#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)
@ -134,10 +146,12 @@
#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3)
#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0)
#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1)
#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2)
#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)
#define PCH_DEV_SLOT_LPC 0x1f
#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3)
#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
@ -151,6 +165,7 @@
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
#define PCH_DEV_GBE _PCH_DEV(LPC, 6)
#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7)
static inline int spi_devfn_to_bus(unsigned int devfn)
{