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src: Fix the warning "type 'hex' are always defined" 

This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.

Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS 2019-01-23 12:04:43 +01:00 committed by Nico Huber
parent d3fa7fa5d8
commit b58e99dfa5
7 changed files with 21 additions and 19 deletions
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2
src/arch/x86/include/arch/memlayout.h
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@ -23,7 +23,7 @@
#define ARCH_STAGE_HAS_BSS_SECTION 0
#endif
#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP
#if (CONFIG_RAMTOP == 0)
# error "CONFIG_RAMTOP not configured"
#endif

2
src/device/pci_ops_mmconf.c
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@ -15,7 +15,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#if !defined(CONFIG_MMCONF_BASE_ADDRESS) || !CONFIG_MMCONF_BASE_ADDRESS
#if (CONFIG_MMCONF_BASE_ADDRESS == 0)
#error "CONFIG_MMCONF_BASE_ADDRESS needs to be non-zero!"
#endif

2
src/drivers/elog/boot_count.c
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@ -30,7 +30,7 @@
# include "option_table.h"
# define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3)
#else
# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) && CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET
# if (CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET != 0)
# define BOOT_COUNT_CMOS_OFFSET CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET
# else
# error "Must configure CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET"

2
src/include/pc80/mc146818rtc.h
View File

@ -198,7 +198,7 @@ unsigned int read_option_lowlevel(unsigned int start, unsigned int size,
# include "option_table.h"
# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3)
#else
# if defined(CONFIG_CMOS_POST_OFFSET) && CONFIG_CMOS_POST_OFFSET
# if (CONFIG_CMOS_POST_OFFSET != 0)
# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET
# else
# error "Must configure CONFIG_CMOS_POST_OFFSET"

2
src/soc/intel/common/block/pcr/pcr.c
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@ -21,7 +21,7 @@
#include <soc/pci_devs.h>
#include <timer.h>
#if !defined(CONFIG_PCR_BASE_ADDRESS) || (CONFIG_PCR_BASE_ADDRESS == 0)
#if (CONFIG_PCR_BASE_ADDRESS == 0)
#error "PCR_BASE_ADDRESS need to be non-zero!"
#endif

12
src/soc/intel/skylake/chip.c
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@ -170,12 +170,12 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->LockDownConfigSpiEiss = 0;
}
/* only replacing preexisting subsys ID defaults when non-zero */
#if defined(CONFIG_SUBSYSTEM_VENDOR_ID) && CONFIG_SUBSYSTEM_VENDOR_ID
params->PchConfigSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID;
#endif
#if defined(CONFIG_SUBSYSTEM_DEVICE_ID) && CONFIG_SUBSYSTEM_DEVICE_ID
params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
#endif
if (CONFIG_SUBSYSTEM_VENDOR_ID != 0)
params->PchConfigSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID;
if (CONFIG_SUBSYSTEM_DEVICE_ID != 0)
params->PchConfigSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
params->WakeConfigWolEnableOverride =
config->WakeConfigWolEnableOverride;
params->WakeConfigPcieWakeFromDeepSx =

18
src/soc/intel/skylake/chip_fsp20.c
View File

@ -391,14 +391,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SpiFlashCfgLockDown = 0;
}
/* only replacing preexisting subsys ID defaults when non-zero */
#if defined(CONFIG_SUBSYSTEM_VENDOR_ID) && CONFIG_SUBSYSTEM_VENDOR_ID
params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID;
params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID;
#endif
#if defined(CONFIG_SUBSYSTEM_DEVICE_ID) && CONFIG_SUBSYSTEM_DEVICE_ID
params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID;
params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
#endif
if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) {
params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID;
params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID;
}
if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) {
params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID;
params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID;
}
params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchPmDeepSxPol = config->PmConfigDeepSxPol;